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Commit e33b0451 authored by Ralf Baechle's avatar Ralf Baechle
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MIPS: PNX8550: Remove support for SOC and JBS and STB810 boards. 

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9b731009
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Showing with 5 additions and 2882 deletions
arch/mips/Kbuild.platforms
View file @ e33b0451
...@@ -20,7 +20,6 @@ platforms += mti-sead3 ...@@ -20,7 +20,6 @@ platforms += mti-sead3
platforms += netlogic platforms += netlogic
platforms += pmc-sierra platforms += pmc-sierra
platforms += pnx833x platforms += pnx833x
platforms += pnx8550
platforms += powertv platforms += powertv
platforms += rb532 platforms += rb532
platforms += sgi-ip22 platforms += sgi-ip22
......
arch/mips/Kconfig
View file @ e33b0451
...@@ -385,16 +385,6 @@ config NXP_STB225 ...@@ -385,16 +385,6 @@ config NXP_STB225
help help
Support for NXP Semiconductors STB225 Development Board. Support for NXP Semiconductors STB225 Development Board.
config PNX8550_JBS
bool "NXP PNX8550 based JBS board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
config PNX8550_STB810
bool "NXP PNX8550 based STB810 board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
config PMC_MSP config PMC_MSP
bool "PMC-Sierra MSP chipsets" bool "PMC-Sierra MSP chipsets"
depends on EXPERIMENTAL depends on EXPERIMENTAL
...@@ -1113,19 +1103,6 @@ config SOC_PNX8335 ...@@ -1113,19 +1103,6 @@ config SOC_PNX8335
bool bool
select SOC_PNX833X select SOC_PNX833X
config PNX8550
bool
select SOC_PNX8550
config SOC_PNX8550
bool
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_GPIO
config SWAP_IO_SPACE config SWAP_IO_SPACE
bool bool
......
arch/mips/configs/pnx8550_jbs_defconfig deleted 100644 → 0
View file @ 9b731009
CONFIG_PNX8550_JBS=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_PCI=y
CONFIG_PM=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_TCP_MD5SIG=y
# CONFIG_IPV6 is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SGI_IOC4=m
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_OFFBOARD=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_HPT366=y
CONFIG_BLK_DEV_IT8213=m
CONFIG_BLK_DEV_TC86C001=m
CONFIG_SCSI=y
CONFIG_SCSI_TGT=m
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_FC_ATTRS=y
CONFIG_ISCSI_TCP=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_PCI=y
CONFIG_8139TOO=y
# CONFIG_8139TOO_PIO is not set
CONFIG_8139TOO_TUNE_TWISTER=y
CONFIG_8139TOO_8129=y
CONFIG_CHELSIO_T3=m
CONFIG_NETXEN_NIC=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_PNX8XXX=y
CONFIG_SERIAL_PNX8XXX_CONSOLE=y
CONFIG_HW_RANDOM=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_DLM=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SLAB=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRC_CCITT=m
arch/mips/configs/pnx8550_stb810_defconfig deleted 100644 → 0
View file @ 9b731009
CONFIG_PNX8550_STB810=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_HOTPLUG is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_PCI=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_OFFBOARD=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_HPT366=y
CONFIG_BLK_DEV_IT8213=m
CONFIG_BLK_DEV_TC86C001=m
CONFIG_SCSI=y
CONFIG_SCSI_TGT=m
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ISCSI_TCP=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_NET_PCI=y
CONFIG_NATSEMI=y
CONFIG_CHELSIO_T3=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_HW_RANDOM=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_DLM=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SLAB=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRC_CCITT=m
arch/mips/include/asm/mach-pnx8550/cm.h deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
* Clock module specific definitions
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef __PNX8550_CM_H
#define __PNX8550_CM_H
#define PNX8550_CM_BASE 0xBBE47000
#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
// Table not complete.....
#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
#define PNX8550_CM_PLL_N_MASK 0x01ff0000
#define PNX8550_CM_PLL_M_MASK 0x00003f00
#define PNX8550_CM_PLL_P_MASK 0x0000000c
#define PNX8550_CM_PLL_PD_MASK 0x00000002
#endif
arch/mips/include/asm/mach-pnx8550/glb.h deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
* PNX8550 global definitions
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef __PNX8550_GLB_H
#define __PNX8550_GLB_H
#define PNX8550_GLB1_BASE 0xBBE63000
#define PNX8550_GLB2_BASE 0xBBE4d000
#define PNX8550_RESET_BASE 0xBBE60000
/* PCI Inta Output Enable Registers */
#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
/* Bit 1:Enable DAC Powerdown
0:DACs are enabled and are working normally
1:DACs are powerdown
*/
#define PNX8550_GLB_DAC_PD 0x2
/* Bit 0:Enable of PCI inta output
0 = Disable PCI inta output
1 = Enable PCI inta output
*/
#define PNX8550_GLB_ENABLE_INTA_O 0x1
/* PCI Direct Mappings */
#define PNX8550_PCIMEM 0x12000000
#define PNX8550_PCIMEM_SIZE 0x08000000
#define PNX8550_PCIIO 0x1c000000
#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
#define PNX8550_PORT_BASE KSEG1
// GPIO def
#define PNX8550_GPIO_BASE 0x1Be00000
#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
#define PNX8550_GPIO_MC_31_BIT 30
#define PNX8550_GPIO_MC_30_BIT 28
#define PNX8550_GPIO_MC_29_BIT 26
#define PNX8550_GPIO_MC_28_BIT 24
#define PNX8550_GPIO_MC_27_BIT 22
#define PNX8550_GPIO_MC_26_BIT 20
#define PNX8550_GPIO_MC_25_BIT 18
#define PNX8550_GPIO_MC_24_BIT 16
#define PNX8550_GPIO_MC_23_BIT 14
#define PNX8550_GPIO_MC_22_BIT 12
#define PNX8550_GPIO_MC_21_BIT 10
#define PNX8550_GPIO_MC_20_BIT 8
#define PNX8550_GPIO_MC_19_BIT 6
#define PNX8550_GPIO_MC_18_BIT 4
#define PNX8550_GPIO_MC_17_BIT 2
#define PNX8550_GPIO_MC_16_BIT 0
#define PNX8550_GPIO_MODE_PRIMOP 0x1
#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
#define PNX8550_GPIO_MODE_OPENDR 0x3
// RESET module
#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
#define PNX8550_RST_REL_MIPS_RST_N 0x8
#define PNX8550_RST_DO_SW_RST 0x4
#define PNX8550_RST_REL_SYS_RST_OUT 0x2
#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
#endif
arch/mips/include/asm/mach-pnx8550/int.h deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
* Interrupt specific definitions
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef __PNX8550_INT_H
#define __PNX8550_INT_H
#define PNX8550_GIC_BASE 0xBBE3E000
#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
// cp0 is two software + six hw exceptions
#define PNX8550_INT_CP0_TOTINT 8
#define PNX8550_INT_CP0_MIN 0
#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
#define MIPS_CPU_GIC_IRQ 2
#define MIPS_CPU_TIMER_IRQ 7
// GIC are 71 exceptions connected to cp0's first hardware exception
#define PNX8550_INT_GIC_TOTINT 71
#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
// Timer are 3 exceptions connected to cp0's 7th hardware exception
#define PNX8550_INT_TIMER_TOTINT 3
#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
#endif
arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h deleted 100644 → 0
View file @ 9b731009
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005 Embedded Alley Solutions, Inc
*/
#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
#define __ASM_MACH_KERNEL_ENTRY_INIT_H
#include <asm/cacheops.h>
#include <asm/addrspace.h>
#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
#define DCACHE_SET_COUNT 128 /* Data cache set count */
#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
.macro kernel_entry_setup
.set push
.set noreorder
/*
* PNX8550 entry point, when running a non compressed
* kernel. When loading a zImage, the head.S code in
* arch/mips/zboot/pnx8550 will init the caches and,
* decompress the kernel, and branch to kernel_entry.
*/
cache_begin: li t0, (1<<28)
mtc0 t0, CP0_STATUS /* cp0 usable */
HAZARD_CP0
mtc0 zero, CP0_CAUSE
HAZARD_CP0
/* Set static virtual to phys address translation and TLB disabled */
mfc0 t0, CP0_CONFIG, 7
HAZARD_CP0
and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
mtc0 t0, CP0_CONFIG, 7
HAZARD_CP0
/* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
init_icache
nop
init_dcache
nop
cachePr4450ICReset
nop
cachePr4450DCReset
nop
/* read ConfigPR into t0 */
mfc0 t0, CP0_CONFIG, 7
HAZARD_CP0
/* enable the TLB */
or t0, (1<<19)
/* disable the ICACHE: at least 10x slower */
/* or t0, (1<<26) */
/* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
/* or t0, (1<<27) */
and t0, CO_CONFIGPR_VALID
/* enable TLB. */
mtc0 t0, CP0_CONFIG, 7
HAZARD_CP0
cache_end:
/* Setup CMEM_0 to MMIO address space, 2MB */
lui t0, 0x1BE0
addi t0, t0, 0x3
mtc0 $8, $22, 4
nop
/* Setup CMEM_1, 128MB */
lui t0, 0x1000
addi t0, t0, 0xf
mtc0 $8, $22, 5
nop
/* Setup CMEM_2, 32MB */
lui t0, 0x1C00
addi t0, t0, 0xb
mtc0 $8, $22, 6
nop
/* Setup CMEM_3, 0MB */
lui t0, 0x0
addi t0, t0, 0x0
mtc0 $8, $22, 7
nop
/* Enable cache */
mfc0 t0, CP0_CONFIG
HAZARD_CP0
and t0, t0, 0xFFFFFFF8
or t0, t0, 3
mtc0 t0, CP0_CONFIG
HAZARD_CP0
.set pop
.endm
.macro init_icache
.set push
.set noreorder
/* Get Cache Configuration */
mfc0 t3, CP0_CONFIG, 1
HAZARD_CP0
/* get cache Line size */
srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
nop
addiu t0, t1, 1
ori t1, zero, 1
sllv t1, t1, t0
/* get max cache Index */
srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
addiu t0, t2, 6
ori t2, zero, 1
sllv t2, t2, t0
/* get max cache way */
srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
addiu t3, t3, 1
/* total no of cache lines */
multu t2, t3 /* max index * max way */
mflo t2
addiu t2, t2, -1
move t0, zero
pr4450_next_instruction_cache_set:
cache Index_Invalidate_I, 0(t0)
addu t0, t0, t1 /* add bytes in a line */
bne t2, zero, pr4450_next_instruction_cache_set
addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
pr4450_instr_cache_invalidated:
.set pop
.endm
.macro init_dcache
.set push
.set noreorder
move t1, zero
/* Store Tag Information */
mtc0 zero, CP0_TAGLO, 0
HAZARD_CP0
mtc0 zero, CP0_TAGHI, 0
HAZARD_CP0
/* Cache size is 16384 = 512 lines x 32 bytes per line */
or t2, zero, (128*4)-1 /* 512 lines */
/* Invalidate all lines */
2:
cache Index_Store_Tag_D, 0(t1)
addiu t2, t2, -1
bne t2, zero, 2b
addiu t1, t1, 32 /* 32 bytes in a line */
.set pop
.endm
.macro cachePr4450ICReset
.set push
.set noreorder
/* Save CP0 status reg on entry; */
/* disable interrupts during cache reset */
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
HAZARD_CP0
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
HAZARD_CP0
or t1, zero, zero /* T1 = starting cache index (0) */
ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
icache_invd_loop:
/* 9 == register t1 */
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
(0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
(1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
/* Initialize the latches in the instruction cache tag */
/* that drive the way selection tri-state bus drivers, by doing a */
/* dummy load while the instruction cache is still disabled. */
/* TODO: Is this needed ? */
la t1, KSEG0 /* T1 = cached memory base address */
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
HAZARD_CP0
.set pop
.endm
.macro cachePr4450DCReset
.set push
.set noreorder
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
HAZARD_CP0
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
HAZARD_CP0
/* Writeback/invalidate entire data cache sets/ways/lines */
or t1, zero, zero /* T1 = starting cache index (0) */
ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
dcache_wbinvd_loop:
/* 9 == register t1 */
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
(3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
/* Initialize the latches in the data cache tag that drive the way
selection tri-state bus drivers, by doing a dummy load while the
data cache is still in the disabled mode. TODO: Is this needed ? */
la t1, KSEG0 /* T1 = cached memory base address */
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
HAZARD_CP0
.set pop
.endm
#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
arch/mips/include/asm/mach-pnx8550/nand.h deleted 100644 → 0
View file @ 9b731009
#ifndef __PNX8550_NAND_H
#define __PNX8550_NAND_H
#define PNX8550_NAND_BASE_ADDR 0x10000000
#define PNX8550_PCIXIO_BASE 0xBBE40000
#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
#define PNX8550_XIO_SEL0_WAIT 0x00000200
#define PNX8550_XIO_SEL0_OFFSET 0x00000020
#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
#define PNX8550_XIO_SEL0_ENAB 0x00000001
#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
(PNX8550_XIO_SEL0_REN_HIGH*0)| \
(PNX8550_XIO_SEL0_REN_LOW*2) | \
(PNX8550_XIO_SEL0_WEN_HIGH*0)| \
(PNX8550_XIO_SEL0_WEN_LOW*2) | \
(PNX8550_XIO_SEL0_WAIT*4) | \
(PNX8550_XIO_SEL0_OFFSET*0) | \
(PNX8550_XIO_SEL0_TYPE_NAND) | \
(PNX8550_XIO_SEL0_SIZE_32MB) | \
(PNX8550_XIO_SEL0_ENAB))
#define PNX8550_GPXIO_PENDING 0x00000200
#define PNX8550_GPXIO_DONE 0x00000100
#define PNX8550_GPXIO_CLR_DONE 0x00000080
#define PNX8550_GPXIO_INIT 0x00000040
#define PNX8550_GPXIO_READ_CMD 0x00000010
#define PNX8550_GPXIO_BEN 0x0000000F
#define PNX8550_XIO_FLASH_64MB 0x00200000
#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
#define PNX8550_XIO_INT_ACK 0x00004000
#define PNX8550_XIO_INT_COMPL 0x00002000
#define PNX8550_XIO_INT_NONSUP 0x00000200
#define PNX8550_XIO_INT_ABORT 0x00000004
#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
#define PNX8550_DMA_CTRL_BURST_8 0x00000000
#define PNX8550_DMA_CTRL_BURST_16 0x00000020
#define PNX8550_DMA_CTRL_BURST_32 0x00000040
#define PNX8550_DMA_CTRL_BURST_64 0x00000060
#define PNX8550_DMA_CTRL_BURST_128 0x00000080
#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
/* see PCI system arch, page 100 for the full list: */
#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
#endif
arch/mips/include/asm/mach-pnx8550/pci.h deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
* PCI specific definitions
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef __PNX8550_PCI_H
#define __PNX8550_PCI_H
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define PCI_CMD_IOR 0x20
#define PCI_CMD_IOW 0x30
#define PCI_CMD_CONFIG_READ 0xa0
#define PCI_CMD_CONFIG_WRITE 0xb0
#define PCI_IO_TIMEOUT 1000
#define PCI_IO_RETRY 5
/* Timeout for IO and CFG accesses.
This is in 1/1024 th of a jiffie(=10ms)
i.e. approx 10us */
#define PCI_IO_JIFFIES_TIMEOUT 40
#define PCI_IO_JIFFIES_SHIFT 10
#define PCI_BYTE_ENABLE_MASK 0x0000000f
#define PCI_CFG_BUS_SHIFT 16
#define PCI_CFG_FUNC_SHIFT 8
#define PCI_CFG_REG_SHIFT 2
#define PCI_BASE 0x1be00000
#define PCI_SETUP 0x00040010
#define PCI_DIS_REQGNT (1<<30)
#define PCI_DIS_REQGNTA (1<<29)
#define PCI_DIS_REQGNTB (1<<28)
#define PCI_D2_SUPPORT (1<<27)
#define PCI_D1_SUPPORT (1<<26)
#define PCI_EN_TA (1<<24)
#define PCI_EN_PCI2MMI (1<<23)
#define PCI_EN_XIO (1<<22)
#define PCI_BASE18_PREF (1<<21)
#define SIZE_16M 0x3
#define SIZE_32M 0x4
#define SIZE_64M 0x5
#define SIZE_128M 0x6
#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
#define PCI_SETUP_BASE18_EN (1<<17)
#define PCI_SETUP_BASE14_PREF (1<<16)
#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
#define PCI_SETUP_BASE14_EN (1<<11)
#define PCI_SETUP_BASE10_PREF (1<<10)
#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
#define PCI_SETUP_CFGMANAGE_EN (1<<1)
#define PCI_SETUP_PCIARB_EN (1<<0)
#define PCI_CTRL 0x040014
#define PCI_SWPB_DCS_PCI (1<<16)
#define PCI_SWPB_PCI_PCI (1<<15)
#define PCI_SWPB_PCI_DCS (1<<14)
#define PCI_REG_WR_POST (1<<13)
#define PCI_XIO_WR_POST (1<<12)
#define PCI_PCI2_WR_POST (1<<13)
#define PCI_PCI1_WR_POST (1<<12)
#define PCI_SERR_SEEN (1<<11)
#define PCI_B10_SPEC_RD (1<<6)
#define PCI_B14_SPEC_RD (1<<5)
#define PCI_B18_SPEC_RD (1<<4)
#define PCI_B10_NOSUBWORD (1<<3)
#define PCI_B14_NOSUBWORD (1<<2)
#define PCI_B18_NOSUBWORD (1<<1)
#define PCI_RETRY_TMREN (1<<0)
#define PCI_BASE1_LO 0x040018
#define PCI_BASE1_HI 0x04001C
#define PCI_BASE2_LO 0x040020
#define PCI_BASE2_HI 0x040024
#define PCI_RDLIFETIM 0x040028
#define PCI_GPPM_ADDR 0x04002C
#define PCI_GPPM_WDAT 0x040030
#define PCI_GPPM_RDAT 0x040034
#define PCI_GPPM_CTRL 0x040038
#define GPPM_DONE (1<<10)
#define INIT_PCI_CYCLE (1<<9)
#define GPPM_CMD(X) (((X)&0xf)<<4)
#define GPPM_BYTEEN(X) ((X)&0xf)
#define PCI_UNLOCKREG 0x04003C
#define UNLOCK_SSID(X) (((X)&0xff)<<8)
#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
#define UNLOCK_MAGIC 0xCA
#define PCI_DEV_VEND_ID 0x040040
#define DEVICE_ID(X) (((X)>>16)&0xffff)
#define VENDOR_ID(X) (((X)&0xffff))
#define PCI_CFG_CMDSTAT 0x040044
#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
#define PCI_CFG_COMMAND(X) ((X)&0xffff)
#define PCI_CLASS_REV 0x040048
#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
#define PCI_REVID(X) ((X)&0xff)
#define PCI_LAT_TMR 0x04004c
#define PCI_BASE10 0x040050
#define PCI_BASE14 0x040054
#define PCI_BASE18 0x040058
#define PCI_SUBSYS_ID 0x04006c
#define PCI_CAP_PTR 0x040074
#define PCI_CFG_MISC 0x04007c
#define PCI_PMC 0x040080
#define PCI_PWR_STATE 0x040084
#define PCI_IO 0x040088
#define PCI_SLVTUNING 0x04008C
#define PCI_DMATUNING 0x040090
#define PCI_DMAEADDR 0x040800
#define PCI_DMAIADDR 0x040804
#define PCI_DMALEN 0x040808
#define PCI_DMACTRL 0x04080C
#define PCI_XIOCTRL 0x040810
#define PCI_SEL0PROF 0x040814
#define PCI_SEL1PROF 0x040818
#define PCI_SEL2PROF 0x04081C
#define PCI_GPXIOADDR 0x040820
#define PCI_NANDCTRLS 0x400830
#define PCI_SEL3PROF 0x040834
#define PCI_SEL4PROF 0x040838
#define PCI_GPXIO_STAT 0x040FB0
#define PCI_GPXIO_IMASK 0x040FB4
#define PCI_GPXIO_ICLR 0x040FB8
#define PCI_GPXIO_ISET 0x040FBC
#define PCI_GPPM_STATUS 0x040FC0
#define GPPM_DONE (1<<10)
#define GPPM_ERR (1<<9)
#define GPPM_MPAR_ERR (1<<8)
#define GPPM_PAR_ERR (1<<7)
#define GPPM_R_MABORT (1<<2)
#define GPPM_R_TABORT (1<<1)
#define PCI_GPPM_IMASK 0x040FC4
#define PCI_GPPM_ICLR 0x040FC8
#define PCI_GPPM_ISET 0x040FCC
#define PCI_DMA_STATUS 0x040FD0
#define PCI_DMA_IMASK 0x040FD4
#define PCI_DMA_ICLR 0x040FD8
#define PCI_DMA_ISET 0x040FDC
#define PCI_ISTATUS 0x040FE0
#define PCI_IMASK 0x040FE4
#define PCI_ICLR 0x040FE8
#define PCI_ISET 0x040FEC
#define PCI_MOD_ID 0x040FFC
/*
* PCI configuration cycle AD bus definition
*/
/* Type 0 */
#define PCI_CFG_TYPE0_REG_SHF 0
#define PCI_CFG_TYPE0_FUNC_SHF 8
/* Type 1 */
#define PCI_CFG_TYPE1_REG_SHF 0
#define PCI_CFG_TYPE1_FUNC_SHF 8
#define PCI_CFG_TYPE1_DEV_SHF 11
#define PCI_CFG_TYPE1_BUS_SHF 16
/*
* Ethernet device DP83816 definition
*/
#define DP83816_IRQ_ETHER 66
#endif
arch/mips/include/asm/mach-pnx8550/uart.h deleted 100644 → 0
View file @ 9b731009
#ifndef __IP3106_UART_H
#define __IP3106_UART_H
#include <int.h>
/* early macros for kgdb use. fixme: clean this up */
#define UART_BASE 0xbbe4a000 /* PNX8550 */
#define PNX8550_UART_PORT0 (UART_BASE)
#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
/* early macros needed for prom/kgdb */
#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
#endif
arch/mips/include/asm/mach-pnx8550/usb.h deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
* USB specific definitions
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef __PNX8550_USB_H
#define __PNX8550_USB_H
/*
* USB Host controller
*/
#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
#define PNX8550_USB_OHCI_OP_LEN 0x1000
#endif
arch/mips/include/asm/mach-pnx8550/war.h deleted 100644 → 0
View file @ 9b731009
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
#define __ASM_MIPS_MACH_PNX8550_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
arch/mips/pci/Makefile
View file @ e33b0451
...@@ -27,7 +27,6 @@ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o ...@@ -27,7 +27,6 @@ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
# #
obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
......
arch/mips/pci/fixup-pnx8550.c deleted 100644 → 0
View file @ 9b731009
/*
* Philips PNX8550 pci fixups.
*
* Copyright 2005 Embedded Alley Solutions, Inc
* source@embeddealley.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mach-pnx8550/pci.h>
#include <asm/mach-pnx8550/int.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
extern char pnx8550_irq_tab[][5];
void __init pcibios_fixup_resources(struct pci_dev *dev)
{
/* no need to fixup IO resources */
}
void __init pcibios_fixup(void)
{
/* nothing to do here */
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return pnx8550_irq_tab[slot][pin];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
arch/mips/pci/ops-pnx8550.c deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
*
* 2.6 port, Embedded Alley Solutions, Inc
*
* Based on:
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <asm/mach-pnx8550/pci.h>
#include <asm/mach-pnx8550/glb.h>
static inline void clear_status(void)
{
unsigned long pci_stat;
pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
}
static inline unsigned int
calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
{
unsigned int addr;
addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
return addr;
}
static int
config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
{
unsigned int flags;
unsigned long loops = 0;
unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
local_irq_save(flags);
/*Clear pending interrupt status */
if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
clear_status();
while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
}
outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
outl(*val, PCI_BASE | PCI_GPPM_WDAT);
outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
PCI_BASE | PCI_GPPM_CTRL);
loops =
((loops_per_jiffy *
PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
while (1) {
if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
if ((pci_cmd == PCI_CMD_IOR) ||
(pci_cmd == PCI_CMD_CONFIG_READ))
*val = inl(PCI_BASE | PCI_GPPM_RDAT);
clear_status();
local_irq_restore(flags);
return PCIBIOS_SUCCESSFUL;
} else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
break;
}
loops--;
if (loops == 0) {
printk("%s : Arbiter Locked.\n", __func__);
}
}
clear_status();
if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
__func__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
pci_cmd);
}
if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
*val = 0xffffffff;
local_irq_restore(flags);
return PCIBIOS_DEVICE_NOT_FOUND;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int
read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
{
unsigned int data = 0;
int err;
if (bus == NULL)
return -1;
err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
switch (where & 0x03) {
case 0:
*val = (unsigned char)(data & 0x000000ff);
break;
case 1:
*val = (unsigned char)((data & 0x0000ff00) >> 8);
break;
case 2:
*val = (unsigned char)((data & 0x00ff0000) >> 16);
break;
case 3:
*val = (unsigned char)((data & 0xff000000) >> 24);
break;
}
return err;
}
static int
read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
{
unsigned int data = 0;
int err;
if (bus == NULL)
return -1;
if (where & 0x01)
return PCIBIOS_BAD_REGISTER_NUMBER;
err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
switch (where & 0x02) {
case 0:
*val = (unsigned short)(data & 0x0000ffff);
break;
case 2:
*val = (unsigned short)((data & 0xffff0000) >> 16);
break;
}
return err;
}
static int
read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
{
int err;
if (bus == NULL)
return -1;
if (where & 0x03)
return PCIBIOS_BAD_REGISTER_NUMBER;
err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
return err;
}
static int
write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
{
unsigned int data = (unsigned int)val;
int err;
if (bus == NULL)
return -1;
switch (where & 0x03) {
case 1:
data = (data << 8);
break;
case 2:
data = (data << 16);
break;
case 3:
data = (data << 24);
break;
default:
break;
}
err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(1 << (where & 3)), &data);
return err;
}
static int
write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
{
unsigned int data = (unsigned int)val;
int err;
if (bus == NULL)
return -1;
if (where & 0x01)
return PCIBIOS_BAD_REGISTER_NUMBER;
switch (where & 0x02) {
case 2:
data = (data << 16);
break;
default:
break;
}
err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
return err;
}
static int
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
{
int err;
if (bus == NULL)
return -1;
if (where & 0x03)
return PCIBIOS_BAD_REGISTER_NUMBER;
err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
return err;
}
static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
{
switch (size) {
case 1: {
u8 _val;
int rc = read_config_byte(bus, devfn, where, &_val);
*val = _val;
return rc;
}
case 2: {
u16 _val;
int rc = read_config_word(bus, devfn, where, &_val);
*val = _val;
return rc;
}
default:
return read_config_dword(bus, devfn, where, val);
}
}
static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
{
switch (size) {
case 1:
return write_config_byte(bus, devfn, where, (u8) val);
case 2:
return write_config_word(bus, devfn, where, (u16) val);
default:
return write_config_dword(bus, devfn, where, val);
}
}
struct pci_ops pnx8550_pci_ops = {
config_read,
config_write
};
arch/mips/pnx8550/Makefile deleted 100644 → 0
View file @ 9b731009
obj-$(CONFIG_SOC_PNX8550) += common/
obj-$(CONFIG_PNX8550_JBS) += jbs/
obj-$(CONFIG_PNX8550_STB810) += stb810/
arch/mips/pnx8550/Platform deleted 100644 → 0
View file @ 9b731009
platform-$(CONFIG_SOC_PNX8550) += pnx8550/
cflags-$(CONFIG_SOC_PNX8550) += \
-I$(srctree)/arch/mips/include/asm/mach-pnx8550
load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
arch/mips/pnx8550/common/Makefile deleted 100644 → 0
View file @ 9b731009
#
# Per Hallsmark, per.hallsmark@mvista.com
#
# ########################################################################
#
# This program is free software; you can distribute it and/or modify it
# under the terms of the GNU General Public License (Version 2) as
# published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
#
# #######################################################################
#
# Makefile for the PNX8550 specific kernel interface routines
# under Linux.
#
obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
obj-$(CONFIG_PCI) += pci.o
arch/mips/pnx8550/common/int.c deleted 100644 → 0
View file @ 9b731009
/*
*
* Copyright (C) 2005 Embedded Alley Solutions, Inc
* Ported to 2.6.
*
* Per Hallsmark, per.hallsmark@mvista.com
* Copyright (C) 2000, 2001 MIPS Technologies, Inc.
* Copyright (C) 2001 Ralf Baechle
*
* Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>
#include <linux/module.h>
#include <asm/io.h>
#include <int.h>
#include <uart.h>
/* default prio for interrupts */
/* first one is a no-no so therefore always prio 0 (disabled) */
static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
1 // 70
};
static void hw0_irqdispatch(int irq)
{
/* find out which interrupt */
irq = PNX8550_GIC_VECTOR_0 >> 3;
if (irq == 0) {
printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
return;
}
do_IRQ(PNX8550_INT_GIC_MIN + irq);
}
static void timer_irqdispatch(int irq)
{
irq = (0x01c0 & read_c0_config7()) >> 6;
if (unlikely(irq == 0)) {
printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
return;
}
if (irq & 0x1)
do_IRQ(PNX8550_INT_TIMER1);
if (irq & 0x2)
do_IRQ(PNX8550_INT_TIMER2);
if (irq & 0x4)
do_IRQ(PNX8550_INT_TIMER3);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP2)
hw0_irqdispatch(2);
else if (pending & STATUSF_IP7) {
if (read_c0_config7() & 0x01c0)
timer_irqdispatch(7);
} else
spurious_interrupt();
}
static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
{
unsigned long status = read_c0_status();
status &= ~((clr_mask & 0xFF) << 8);
status |= (set_mask & 0xFF) << 8;
write_c0_status(status);
}
static inline void mask_gic_int(unsigned int irq_nr)
{
/* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
}
static inline void unmask_gic_int(unsigned int irq_nr)
{
/* set prio mask to lower four bits and enable interrupt */
PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
}
static inline void mask_irq(struct irq_data *d)
{
unsigned int irq_nr = d->irq;
if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
modify_cp0_intmask(1 << irq_nr, 0);
} else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_GIC_MAX)) {
mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
} else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_TIMER_MAX)) {
modify_cp0_intmask(1 << 7, 0);
} else {
printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
}
}
static inline void unmask_irq(struct irq_data *d)
{
unsigned int irq_nr = d->irq;
if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
modify_cp0_intmask(0, 1 << irq_nr);
} else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_GIC_MAX)) {
unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
} else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_TIMER_MAX)) {
modify_cp0_intmask(0, 1 << 7);
} else {
printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
}
}
int pnx8550_set_gic_priority(int irq, int priority)
{
int gic_irq = irq-PNX8550_INT_GIC_MIN;
int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
gic_prio[gic_irq] = priority;
PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
return prev_priority;
}
static struct irq_chip level_irq_type = {
.name = "PNX Level IRQ",
.irq_mask = mask_irq,
.irq_unmask = unmask_irq,
};
static struct irqaction gic_action = {
.handler = no_action,
.flags = IRQF_NO_THREAD,
.name = "GIC",
};
static struct irqaction timer_action = {
.handler = no_action,
.flags = IRQF_TIMER,
.name = "Timer",
};
void __init arch_init_irq(void)
{
int i;
int configPR;
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
/* init of GIC/IPC interrupts */
/* should be done before cp0 since cp0 init enables the GIC int */
for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
int gic_int_line = i - PNX8550_INT_GIC_MIN;
if (gic_int_line == 0 )
continue; // don't fiddle with int 0
/*
* enable change of TARGET, ENABLE and ACTIVE_LOW bits
* set TARGET 0 to route through hw0 interrupt
* set ACTIVE_LOW 0 active high (correct?)
*
* We really should setup an interrupt description table
* to do this nicely.
* Note, PCI INTA is active low on the bus, but inverted
* in the GIC, so to us it's active high.
*/
PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
}
/* Priority level 0 */
PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
/* Set int vector table address */
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
handle_level_irq);
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
/* init of Timer interrupts */
for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
/* Stop Timer 1-3 */
configPR = read_c0_config7();
configPR |= 0x00000038;
write_c0_config7(configPR);
irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
handle_level_irq);
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
}
EXPORT_SYMBOL(pnx8550_set_gic_priority);
arch/mips/pnx8550/common/pci.c deleted 100644 → 0
View file @ 9b731009
/*
*
* BRIEF MODULE DESCRIPTION
*
* Author: source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <pci.h>
#include <glb.h>
#include <nand.h>
static struct resource pci_io_resource = {
.start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */
.end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
.name = "pci IO space",
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.start = PNX8550_PCIMEM,
.end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
.name = "pci memory space",
.flags = IORESOURCE_MEM
};
extern struct pci_ops pnx8550_pci_ops;
static struct pci_controller pnx8550_controller = {
.pci_ops = &pnx8550_pci_ops,
.io_map_base = PNX8550_PORT_BASE,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
};
/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
static inline unsigned long get_system_mem_size(void)
{
/* Read IP2031_RANK0_ADDR_LO */
unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
/* Read IP2031_RANK1_ADDR_HI */
unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
return dram_r1_hi - dram_r0_lo + 1;
}
static int __init pnx8550_pci_setup(void)
{
int pci_mem_code;
int mem_size = get_system_mem_size() >> 20;
/* Clear the Global 2 Register, PCI Inta Output Enable Registers
Bit 1:Enable DAC Powerdown
-> 0:DACs are enabled and are working normally
1:DACs are powerdown
Bit 0:Enable of PCI inta output
-> 0 = Disable PCI inta output
1 = Enable PCI inta output
*/
PNX8550_GLB2_ENAB_INTA_O = 0;
/* Calc the PCI mem size code */
if (mem_size >= 128)
pci_mem_code = SIZE_128M;
else if (mem_size >= 64)
pci_mem_code = SIZE_64M;
else if (mem_size >= 32)
pci_mem_code = SIZE_32M;
else
pci_mem_code = SIZE_16M;
/* Set PCI_XIO registers */
outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
/* Send memory transaction via PCI_BASE2 */
outl(0x00000001, PCI_BASE | PCI_IO);
/* Unlock the setup register */
outl(0xca, PCI_BASE | PCI_UNLOCKREG);
/*
* BAR0 of PNX8550 (pci base 10) must be zero in order for ide
* to work, and in order for bus_to_baddr to work without any
* hacks.
*/
outl(0x00000000, PCI_BASE | PCI_BASE10);
/*
*These two bars are set by default or the boot code.
* However, it's safer to set them here so we're not boot
* code dependent.
*/
outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
outl(PCI_EN_TA |
PCI_EN_PCI2MMI |
PCI_EN_XIO |
PCI_SETUP_BASE18_SIZE(SIZE_32M) |
PCI_SETUP_BASE18_EN |
PCI_SETUP_BASE14_EN |
PCI_SETUP_BASE10_PREF |
PCI_SETUP_BASE10_SIZE(pci_mem_code) |
PCI_SETUP_CFGMANAGE_EN |
PCI_SETUP_PCIARB_EN,
PCI_BASE |
PCI_SETUP); /* PCI_SETUP */
outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
register_pci_controller(&pnx8550_controller);
return 0;
}
arch_initcall(pnx8550_pci_setup);
arch/mips/pnx8550/common/platform.c deleted 100644 → 0
View file @ 9b731009
/*
* Platform device support for NXP PNX8550 SoCs
*
* Copyright 2005, Embedded Alley Solutions, Inc
*
* Based on arch/mips/au1000/common/platform.c
* Platform device support for Au1x00 SoCs.
*
* Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/resource.h>
#include <linux/serial.h>
#include <linux/serial_pnx8xxx.h>
#include <linux/platform_device.h>
#include <linux/usb/ohci_pdriver.h>
#include <int.h>
#include <usb.h>
#include <uart.h>
static struct resource pnx8550_usb_ohci_resources[] = {
[0] = {
.start = PNX8550_USB_OHCI_OP_BASE,
.end = PNX8550_USB_OHCI_OP_BASE +
PNX8550_USB_OHCI_OP_LEN,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX8550_INT_USB,
.end = PNX8550_INT_USB,
.flags = IORESOURCE_IRQ,
},
};
static struct resource pnx8550_uart_resources[] = {
[0] = {
.start = PNX8550_UART_PORT0,
.end = PNX8550_UART_PORT0 + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX8550_UART_INT(0),
.end = PNX8550_UART_INT(0),
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = PNX8550_UART_PORT1,
.end = PNX8550_UART_PORT1 + 0xfff,
.flags = IORESOURCE_MEM,
},
[3] = {
.start = PNX8550_UART_INT(1),
.end = PNX8550_UART_INT(1),
.flags = IORESOURCE_IRQ,
},
};
struct pnx8xxx_port pnx8xxx_ports[] = {
[0] = {
.port = {
.type = PORT_PNX8XXX,
.iotype = UPIO_MEM,
.membase = (void __iomem *)PNX8550_UART_PORT0,
.mapbase = PNX8550_UART_PORT0,
.irq = PNX8550_UART_INT(0),
.uartclk = 3692300,
.fifosize = 16,
.flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
},
[1] = {
.port = {
.type = PORT_PNX8XXX,
.iotype = UPIO_MEM,
.membase = (void __iomem *)PNX8550_UART_PORT1,
.mapbase = PNX8550_UART_PORT1,
.irq = PNX8550_UART_INT(1),
.uartclk = 3692300,
.fifosize = 16,
.flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
},
};
/* The dmamask must be set for OHCI to work */
static u64 ohci_dmamask = DMA_BIT_MASK(32);
static u64 uart_dmamask = DMA_BIT_MASK(32);
static int pnx8550_usb_ohci_power_on(struct platform_device *pdev)
{
/*
* Set register CLK48CTL to enable and 48MHz
*/
outl(0x00000003, PCI_BASE | 0x0004770c);
/*
* Set register CLK12CTL to enable and 48MHz
*/
outl(0x00000003, PCI_BASE | 0x00047710);
udelay(100);
return 0;
}
static void pnx8550_usb_ohci_power_off(struct platform_device *pdev)
{
udelay(10);
}
static struct usb_ohci_pdata pnx8550_usb_ohci_pdata = {
.power_on = pnx8550_usb_ohci_power_on,
.power_off = pnx8550_usb_ohci_power_off,
};
static struct platform_device pnx8550_usb_ohci_device = {
.name = "ohci-platform",
.id = -1,
.dev = {
.dma_mask = &ohci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &pnx8550_usb_ohci_pdata,
},
.num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
.resource = pnx8550_usb_ohci_resources,
};
static struct platform_device pnx8550_uart_device = {
.name = "pnx8xxx-uart",
.id = -1,
.dev = {
.dma_mask = &uart_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = pnx8xxx_ports,
},
.num_resources = ARRAY_SIZE(pnx8550_uart_resources),
.resource = pnx8550_uart_resources,
};
static struct platform_device *pnx8550_platform_devices[] __initdata = {
&pnx8550_usb_ohci_device,
&pnx8550_uart_device,
};
static int __init pnx8550_platform_init(void)
{
return platform_add_devices(pnx8550_platform_devices,
ARRAY_SIZE(pnx8550_platform_devices));
}
arch_initcall(pnx8550_platform_init);
arch/mips/pnx8550/common/proc.c deleted 100644 → 0
View file @ 9b731009
/*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>
#include <asm/io.h>
#include <int.h>
#include <uart.h>
static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
{
int len = 0;
int configPR = read_c0_config7();
if (offset==0) {
len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
read_c0_count(), read_c0_compare(),
(configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
read_c0_count2(), read_c0_compare2(),
(configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
read_c0_count3(), read_c0_compare3(),
(configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
}
return len;
}
static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
{
int len = 0;
if (offset==0) {
len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
}
return len;
}
static struct proc_dir_entry* pnx8550_dir;
static struct proc_dir_entry* pnx8550_timers;
static struct proc_dir_entry* pnx8550_registers;
static int pnx8550_proc_init( void )
{
// Create /proc/pnx8550
pnx8550_dir = proc_mkdir("pnx8550", NULL);
if (!pnx8550_dir) {
printk(KERN_ERR "Can't create pnx8550 proc dir\n");
return -1;
}
// Create /proc/pnx8550/timers
pnx8550_timers = create_proc_read_entry(
"timers",
0,
pnx8550_dir,
pnx8550_timers_read,
NULL);
if (!pnx8550_timers)
printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
// Create /proc/pnx8550/registers
pnx8550_registers = create_proc_read_entry(
"registers",
0,
pnx8550_dir,
pnx8550_registers_read,
NULL);
if (!pnx8550_registers)
printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
return 0;
}
__initcall(pnx8550_proc_init);
arch/mips/pnx8550/common/prom.c deleted 100644 → 0
View file @ 9b731009
/*
*
* Per Hallsmark, per.hallsmark@mvista.com
*
* Based on jmr3927/common/prom.c
*
* 2004 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/serial_pnx8xxx.h>
#include <asm/bootinfo.h>
#include <uart.h>
/* #define DEBUG_CMDLINE */
extern int prom_argc;
extern char **prom_argv, **prom_envp;
typedef struct
{
char *name;
/* char *val; */
}t_env_var;
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
void __init prom_init_cmdline(void)
{
int i;
arcs_cmdline[0] = '\0';
for (i = 0; i < prom_argc; i++) {
strcat(arcs_cmdline, prom_argv[i]);
strcat(arcs_cmdline, " ");
}
}
char *prom_getenv(char *envname)
{
/*
* Return a pointer to the given environment variable.
* Environment variables are stored in the form of "memsize=64".
*/
t_env_var *env = (t_env_var *)prom_envp;
int i;
i = strlen(envname);
while(env->name) {
if(strncmp(envname, env->name, i) == 0) {
return(env->name + strlen(envname) + 1);
}
env++;
}
return(NULL);
}
inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
return c - '0';
if(c >= 'a' && c <= 'f')
return c - 'a' + 10;
if(c >= 'A' && c <= 'F')
return c - 'A' + 10;
return 0; /* foo */
}
inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
int i;
for(i = 0; i < 6; i++) {
unsigned char num;
if((*str == '.') || (*str == ':'))
str++;
num = str2hexnum(*str++) << 4;
num |= (str2hexnum(*str++));
ea[i] = num;
}
}
int get_ethernet_addr(char *ethernet_addr)
{
char *ethaddr_str;
ethaddr_str = prom_getenv("ethaddr");
if (!ethaddr_str) {
printk("ethaddr not set in boot prom\n");
return -1;
}
str2eaddr(ethernet_addr, ethaddr_str);
return 0;
}
void __init prom_free_prom_memory(void)
{
}
extern int pnx8550_console_port;
/* used by early printk */
void prom_putchar(char c)
{
if (pnx8550_console_port != -1) {
/* Wait until FIFO not full */
while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16)
;
/* Send one char */
ip3106_fifo(UART_BASE, pnx8550_console_port) = c;
}
}
EXPORT_SYMBOL(get_ethernet_addr);
EXPORT_SYMBOL(str2eaddr);
arch/mips/pnx8550/common/reset.c deleted 100644 → 0
View file @ 9b731009
/*.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Reset the PNX8550 board.
*
*/
#include <linux/kernel.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <glb.h>
void pnx8550_machine_restart(char *command)
{
PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
}
void pnx8550_machine_halt(void)
{
while (1) {
if (cpu_wait)
cpu_wait();
}
}
arch/mips/pnx8550/common/setup.c deleted 100644 → 0
View file @ 9b731009
/*
*
* 2.6 port, Embedded Alley Solutions, Inc
*
* Based on Per Hallsmark, per.hallsmark@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/serial_pnx8xxx.h>
#include <linux/pm.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/pgtable.h>
#include <asm/time.h>
#include <glb.h>
#include <int.h>
#include <pci.h>
#include <uart.h>
#include <nand.h>
extern void __init board_setup(void);
extern void pnx8550_machine_restart(char *);
extern void pnx8550_machine_halt(void);
extern struct resource ioport_resource;
extern struct resource iomem_resource;
extern char *prom_getcmdline(void);
struct resource standard_io_resources[] = {
{
.start = 0x00,
.end = 0x1f,
.name = "dma1",
.flags = IORESOURCE_BUSY
}, {
.start = 0x40,
.end = 0x5f,
.name = "timer",
.flags = IORESOURCE_BUSY
}, {
.start = 0x80,
.end = 0x8f,
.name = "dma page reg",
.flags = IORESOURCE_BUSY
}, {
.start = 0xc0,
.end = 0xdf,
.name = "dma2",
.flags = IORESOURCE_BUSY
},
};
#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
unsigned long get_system_mem_size(void)
{
/* Read IP2031_RANK0_ADDR_LO */
unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
/* Read IP2031_RANK1_ADDR_HI */
unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
return dram_r1_hi - dram_r0_lo + 1;
}
int pnx8550_console_port = -1;
void __init plat_mem_setup(void)
{
int i;
char* argptr;
board_setup(); /* board specific setup */
_machine_restart = pnx8550_machine_restart;
_machine_halt = pnx8550_machine_halt;
pm_power_off = pnx8550_machine_halt;
/* Clear the Global 2 Register, PCI Inta Output Enable Registers
Bit 1:Enable DAC Powerdown
-> 0:DACs are enabled and are working normally
1:DACs are powerdown
Bit 0:Enable of PCI inta output
-> 0 = Disable PCI inta output
1 = Enable PCI inta output
*/
PNX8550_GLB2_ENAB_INTA_O = 0;
/* IO/MEM resources. */
set_io_port_base(PNX8550_PORT_BASE);
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
/* Request I/O space for devices on this board */
for (i = 0; i < STANDARD_IO_RESOURCES; i++)
request_resource(&ioport_resource, standard_io_resources + i);
/* Place the Mode Control bit for GPIO pin 16 in primary function */
/* Pin 16 is used by UART1, UA1_TX */
outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
(PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
PNX8550_GPIO_MC1);
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
argptr += strlen("console=ttyS");
pnx8550_console_port = *argptr == '0' ? 0 : 1;
/* We must initialize the UART (console) before early printk */
/* Set LCR to 8-bit and BAUD to 38400 (no 5) */
ip3106_lcr(UART_BASE, pnx8550_console_port) =
PNX8XXX_UART_LCR_8BIT;
ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
}
}
arch/mips/pnx8550/common/time.c deleted 100644 → 0
View file @ 9b731009
/*
* Copyright 2001, 2002, 2003 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
*
* Common time service routines for MIPS machines. See
* Documents/MIPS/README.txt.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/time.h>
#include <linux/timer.h>
#include <linux/smp.h>
#include <linux/kernel_stat.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <asm/hardirq.h>
#include <asm/div64.h>
#include <asm/debug.h>
#include <int.h>
#include <cm.h>
static unsigned long cpj;
static cycle_t hpt_read(struct clocksource *cs)
{
return read_c0_count2();
}
static struct clocksource pnx_clocksource = {
.name = "pnx8xxx",
.rating = 200,
.read = hpt_read,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
/* clear MATCH, signal the event */
c->event_handler(c);
return IRQ_HANDLED;
}
static struct irqaction pnx8xxx_timer_irq = {
.handler = pnx8xxx_timer_interrupt,
.flags = IRQF_PERCPU | IRQF_TIMER,
.name = "pnx8xxx_timer",
};
static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
{
/* Timer 2 clear interrupt */
write_c0_compare2(-1);
return IRQ_HANDLED;
}
static struct irqaction monotonic_irqaction = {
.handler = monotonic_interrupt,
.flags = IRQF_TIMER,
.name = "Monotonic timer",
};
static int pnx8xxx_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
write_c0_compare(delta);
return 0;
}
static struct clock_event_device pnx8xxx_clockevent = {
.name = "pnx8xxx_clockevent",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = pnx8xxx_set_next_event,
};
static inline void timer_ack(void)
{
write_c0_compare(cpj);
}
__init void plat_time_init(void)
{
unsigned int configPR;
unsigned int n;
unsigned int m;
unsigned int p;
unsigned int pow2p;
pnx8xxx_clockevent.cpumask = cpu_none_mask;
clockevents_register_device(&pnx8xxx_clockevent);
clocksource_register(&pnx_clocksource);
/* Timer 1 start */
configPR = read_c0_config7();
configPR &= ~0x00000008;
write_c0_config7(configPR);
/* Timer 2 start */
configPR = read_c0_config7();
configPR &= ~0x00000010;
write_c0_config7(configPR);
/* Timer 3 stop */
configPR = read_c0_config7();
configPR |= 0x00000020;
write_c0_config7(configPR);
/* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
/* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
pow2p = (1 << p);
db_assert(m != 0 && pow2p != 0);
/*
* Compute the frequency as in the PNX8550 User Manual 1.0, p.186
* (a.k.a. 8-10). Divide by HZ for a timer offset that results in
* HZ timer interrupts per second.
*/
mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
cpj = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
write_c0_count(0);
timer_ack();
/* Setup Timer 2 */
write_c0_count2(0);
write_c0_compare2(0xffffffff);
setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
}
arch/mips/pnx8550/jbs/Makefile deleted 100644 → 0
View file @ 9b731009
# Makefile for the NXP JBS Board.
obj-y := init.o board_setup.o irqmap.o
arch/mips/pnx8550/jbs/board_setup.c deleted 100644 → 0
View file @ 9b731009
/*
* JBS Specific board startup routines.
*
* Copyright 2005, Embedded Alley Solutions, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/mc146818rtc.h>
#include <linux/delay.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/pgtable.h>
#include <glb.h>
/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t")
void __init board_setup(void)
{
unsigned long configpr;
configpr = read_c0_config7();
configpr |= (1<<19); /* enable tlb */
write_c0_config7(configpr);
BARRIER;
}
arch/mips/pnx8550/jbs/init.c deleted 100644 → 0
View file @ 9b731009
/*
*
* Copyright 2005 Embedded Alley Solutions, Inc
* source@embeddedalley.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <linux/string.h>
#include <linux/kernel.h>
int prom_argc;
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
const char *get_system_type(void)
{
return "NXP PNX8550/JBS";
}
void __init prom_init(void)
{
unsigned long memsize;
//memsize = 0x02800000; /* Trimedia uses memory above */
memsize = 0x08000000; /* Trimedia uses memory above */
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
arch/mips/pnx8550/jbs/irqmap.c deleted 100644 → 0
View file @ 9b731009
/*
* NXP JBS board irqmap.
*
* Copyright 2005 Embedded Alley Solutions, Inc
* source@embeddealley.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <int.h>
char pnx8550_irq_tab[][5] __initdata = {
[8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
[9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
[17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
};
arch/mips/pnx8550/stb810/Makefile deleted 100644 → 0
View file @ 9b731009
# Makefile for the NXP STB810 Board.
obj-y := prom_init.o board_setup.o irqmap.o
arch/mips/pnx8550/stb810/board_setup.c deleted 100644 → 0
View file @ 9b731009
/*
* STB810 specific board startup routines.
*
* Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/mc146818rtc.h>
#include <linux/delay.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/pgtable.h>
#include <glb.h>
void __init board_setup(void)
{
unsigned long configpr;
configpr = read_c0_config7();
configpr |= (1<<19); /* enable tlb */
write_c0_config7(configpr);
}
arch/mips/pnx8550/stb810/irqmap.c deleted 100644 → 0
View file @ 9b731009
/*
* NXP STB810 board irqmap.
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <int.h>
char pnx8550_irq_tab[][5] __initdata = {
[8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
[9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
[10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
};
arch/mips/pnx8550/stb810/prom_init.c deleted 100644 → 0
View file @ 9b731009
/*
* STB810 specific prom routines
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <linux/string.h>
#include <linux/kernel.h>
int prom_argc;
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
const char *get_system_type(void)
{
return "NXP PNX8950/STB810";
}
void __init prom_init(void)
{
unsigned long memsize;
prom_argc = (int) fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
prom_init_cmdline();
memsize = 0x08000000; /* Trimedia uses memory above */
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
drivers/tty/serial/Kconfig
View file @ e33b0451
...@@ -716,19 +716,19 @@ config SERIAL_SH_SCI_DMA ...@@ -716,19 +716,19 @@ config SERIAL_SH_SCI_DMA
config SERIAL_PNX8XXX config SERIAL_PNX8XXX
bool "Enable PNX8XXX SoCs' UART Support" bool "Enable PNX8XXX SoCs' UART Support"
depends on SOC_PNX8550 || SOC_PNX833X depends on SOC_PNX833X
select SERIAL_CORE select SERIAL_CORE
help help
If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 If you have a MIPS-based Philips SoC such as PNX8330 and you want
and you want to use serial ports, say Y. Otherwise, say N. to use serial ports, say Y. Otherwise, say N.
config SERIAL_PNX8XXX_CONSOLE config SERIAL_PNX8XXX_CONSOLE
bool "Enable PNX8XX0 serial console" bool "Enable PNX8XX0 serial console"
depends on SERIAL_PNX8XXX depends on SERIAL_PNX8XXX
select SERIAL_CORE_CONSOLE select SERIAL_CORE_CONSOLE
help help
If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 If you have a MIPS-based Philips SoC such as PNX8330 and you want
and you want to use serial console, say Y. Otherwise, say N. to use serial console, say Y. Otherwise, say N.
config SERIAL_HS_LPC32XX config SERIAL_HS_LPC32XX
tristate "LPC32XX high speed serial port support" tristate "LPC32XX high speed serial port support"
......
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