Commit e35b1350 authored by Bruno Herrera's avatar Bruno Herrera Committed by Felipe Balbi

usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

This patch introduces a new parameter to activate USB OTG HS/FS core
embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register
to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.
Acked-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarBruno Herrera <bruherrera@gmail.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent f87599a0
...@@ -423,6 +423,10 @@ enum dwc2_ep0_state { ...@@ -423,6 +423,10 @@ enum dwc2_ep0_state {
* needed. * needed.
* 0 - No (default) * 0 - No (default)
* 1 - Yes * 1 - Yes
* @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
* register.
* 0 - Deactivate the transceiver (default)
* 1 - Activate the transceiver
* @g_dma: Enables gadget dma usage (default: autodetect). * @g_dma: Enables gadget dma usage (default: autodetect).
* @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
* @g_rx_fifo_size: The periodic rx fifo size for the device, in * @g_rx_fifo_size: The periodic rx fifo size for the device, in
...@@ -477,6 +481,7 @@ struct dwc2_core_params { ...@@ -477,6 +481,7 @@ struct dwc2_core_params {
bool uframe_sched; bool uframe_sched;
bool external_id_pin_ctl; bool external_id_pin_ctl;
bool hibernation; bool hibernation;
bool activate_stm_fs_transceiver;
u16 max_packet_count; u16 max_packet_count;
u32 max_transfer_size; u32 max_transfer_size;
u32 ahbcfg; u32 ahbcfg;
......
...@@ -121,7 +121,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) ...@@ -121,7 +121,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
{ {
u32 usbcfg, i2cctl; u32 usbcfg, ggpio, i2cctl;
int retval = 0; int retval = 0;
/* /*
...@@ -145,6 +145,19 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ...@@ -145,6 +145,19 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
return retval; return retval;
} }
} }
if (hsotg->params.activate_stm_fs_transceiver) {
ggpio = dwc2_readl(hsotg->regs + GGPIO);
if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
dev_dbg(hsotg->dev, "Activating transceiver\n");
/*
* STM32F4x9 uses the GGPIO register as general
* core configuration register.
*/
ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
dwc2_writel(ggpio, hsotg->regs + GGPIO);
}
}
} }
/* /*
......
...@@ -225,6 +225,8 @@ ...@@ -225,6 +225,8 @@
#define GPVNDCTL HSOTG_REG(0x0034) #define GPVNDCTL HSOTG_REG(0x0034)
#define GGPIO HSOTG_REG(0x0038) #define GGPIO HSOTG_REG(0x0038)
#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
#define GUID HSOTG_REG(0x003c) #define GUID HSOTG_REG(0x003c)
#define GSNPSID HSOTG_REG(0x0040) #define GSNPSID HSOTG_REG(0x0040)
#define GHWCFG1 HSOTG_REG(0x0044) #define GHWCFG1 HSOTG_REG(0x0044)
......
...@@ -120,6 +120,22 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) ...@@ -120,6 +120,22 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
} }
static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = &hsotg->params;
p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
p->speed = DWC2_SPEED_PARAM_FULL;
p->host_rx_fifo_size = 128;
p->host_nperio_tx_fifo_size = 96;
p->host_perio_tx_fifo_size = 96;
p->max_packet_count = 256;
p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
p->i2c_enable = false;
p->uframe_sched = false;
p->activate_stm_fs_transceiver = true;
}
const struct of_device_id dwc2_of_match_table[] = { const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
...@@ -133,6 +149,9 @@ const struct of_device_id dwc2_of_match_table[] = { ...@@ -133,6 +149,9 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "amlogic,meson-gxbb-usb", { .compatible = "amlogic,meson-gxbb-usb",
.data = dwc2_set_amlogic_params }, .data = dwc2_set_amlogic_params },
{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
{ .compatible = "st,stm32f4x9-fsotg",
.data = dwc2_set_stm32f4x9_fsotg_params },
{ .compatible = "st,stm32f4x9-hsotg" },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, dwc2_of_match_table); MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
......
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