Commit e42569d0 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher

drm/amd/pm: Modify mode2 msg sequence on aldebaran

v1: During mode2 reset, PCI space is lost after message is sent.
Restore PCI space before waiting for response from firmware.

v2: Move mode2 sequence to aldebaran and update PMFW version.
Handle generic sequence in smu13 without PMFW version check.
Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e6c6338f
...@@ -1432,6 +1432,57 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, ...@@ -1432,6 +1432,57 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_1); return sizeof(struct gpu_metrics_v1_1);
} }
int aldebaran_mode2_reset(struct smu_context *smu)
{
u32 smu_version;
int ret = 0, index;
struct amdgpu_device *adev = smu->adev;
int timeout = 10;
smu_cmn_get_smc_version(smu, NULL, &smu_version);
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_GfxDeviceDriverReset);
mutex_lock(&smu->message_lock);
if (smu_version >= 0x00441400) {
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
/* This is similar to FLR, wait till max FLR timeout */
msleep(100);
dev_dbg(smu->adev->dev, "restore config space...\n");
/* Restore the config space saved during init */
amdgpu_device_load_pci_state(adev->pdev);
dev_dbg(smu->adev->dev, "wait for reset ack\n");
while (ret == -ETIME && timeout) {
ret = smu_cmn_wait_for_response(smu);
/* Wait a bit more time for getting ACK */
if (ret == -ETIME) {
--timeout;
usleep_range(500, 1000);
continue;
}
if (ret != 1) {
dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
SMU_RESET_MODE_2, ret);
goto out;
}
}
} else {
dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
smu_version);
}
if (ret == 1)
ret = 0;
out:
mutex_unlock(&smu->message_lock);
return ret;
}
static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
{ {
#if 0 #if 0
...@@ -1530,8 +1581,8 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { ...@@ -1530,8 +1581,8 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
.mode1_reset_is_support = aldebaran_is_mode1_reset_supported, .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
.mode2_reset_is_support = aldebaran_is_mode2_reset_supported, .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
.mode1_reset = smu_v13_0_mode1_reset, .mode1_reset = smu_v13_0_mode1_reset,
.mode2_reset = smu_v13_0_mode2_reset,
.set_mp1_state = aldebaran_set_mp1_state, .set_mp1_state = aldebaran_set_mp1_state,
.mode2_reset = aldebaran_mode2_reset,
}; };
void aldebaran_set_ppt_funcs(struct smu_context *smu) void aldebaran_set_ppt_funcs(struct smu_context *smu)
......
...@@ -1376,17 +1376,14 @@ int smu_v13_0_mode1_reset(struct smu_context *smu) ...@@ -1376,17 +1376,14 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
int smu_v13_0_mode2_reset(struct smu_context *smu) int smu_v13_0_mode2_reset(struct smu_context *smu)
{ {
u32 smu_version; int ret;
int ret = 0;
struct amdgpu_device *adev = smu->adev; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
smu_cmn_get_smc_version(smu, NULL, &smu_version); SMU_RESET_MODE_2, NULL);
if (smu_version >= 0x00440700) /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
else
dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", smu_version);
/*TODO: mode2 reset wait time should be shorter, will modify it later*/
if (!ret) if (!ret)
msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
return ret; return ret;
} }
......
...@@ -76,7 +76,7 @@ static void smu_cmn_read_arg(struct smu_context *smu, ...@@ -76,7 +76,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
} }
static int smu_cmn_wait_for_response(struct smu_context *smu) int smu_cmn_wait_for_response(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev; struct amdgpu_device *adev = smu->adev;
uint32_t cur_value, i, timeout = adev->usec_timeout * 10; uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
......
...@@ -37,6 +37,8 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, ...@@ -37,6 +37,8 @@ int smu_cmn_send_smc_msg(struct smu_context *smu,
enum smu_message_type msg, enum smu_message_type msg,
uint32_t *read_arg); uint32_t *read_arg);
int smu_cmn_wait_for_response(struct smu_context *smu);
int smu_cmn_to_asic_specific_index(struct smu_context *smu, int smu_cmn_to_asic_specific_index(struct smu_context *smu,
enum smu_cmn2asic_mapping_type type, enum smu_cmn2asic_mapping_type type,
uint32_t index); uint32_t index);
......
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