Commit e62e3acd authored by Sibi Sankar's avatar Sibi Sankar Committed by Bjorn Andersson

dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs

7C retail devices using MSA based boot will result in a fuse combination
which will prevent accesses to MSS PERPH register space where the mpss
clocks and halt-nav reside. However accesses to conn_box_spare0 in TCSR
register space is still permitted so rename the binding appropriately to
qcom,spare-regs and drop all accesses to the MPSS PERPH register space.
Tested-by: default avatarEvan Green <evgreen@chromium.org>
Signed-off-by: default avatarSibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200415145110.20624-2-sibis@codeaurora.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent f6da4831
......@@ -79,7 +79,7 @@ on the Qualcomm Hexagon core.
"snoc_axi", "mnoc_axi", "qdss"
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"mss_crypto", "mss_nav", "nav"
"nav"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
......@@ -181,16 +181,12 @@ For the compatible string below the following supplies are required:
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
- qcom,halt-nav-regs:
- qcom,spare-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to a list of 2 phandles with one offset each for
the modem sub-system running on SC7180 SoC. The first
phandle reference is to the mss clock node followed by the
offset within register space for nav halt register. The
second phandle reference is to a syscon representing TCSR
followed by the offset within syscon for conn_box_spare0
register.
Definition: a phandle reference to a syscon representing TCSR followed
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
= SUBNODES:
The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
......
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