Commit e69fd509 authored by Lubomir Rintel's avatar Lubomir Rintel

ARM: mmp: map the PGU as well

The MMP2 and later includes a system control unit in this area. We'll need
that to initialize the secondary core on MMP3.
Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
parent df8bf2d8
......@@ -20,6 +20,10 @@
#define AXI_VIRT_BASE IOMEM(0xfe200000)
#define AXI_PHYS_SIZE 0x00200000
#define PGU_PHYS_BASE 0xe0000000
#define PGU_VIRT_BASE IOMEM(0xfe400000)
#define PGU_PHYS_SIZE 0x00100000
/* Static Memory Controller - Chip Select 0 and 1 */
#define SMC_CS0_PHYS_BASE 0x80000000
#define SMC_CS0_PHYS_SIZE 0x10000000
......@@ -38,4 +42,7 @@
#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
#define CIU_REG(x) (CIU_VIRT_BASE + (x))
#define SCU_VIRT_BASE (PGU_VIRT_BASE)
#define SCU_REG(x) (SCU_VIRT_BASE + (x))
#endif /* __ASM_MACH_ADDR_MAP_H */
......@@ -36,6 +36,15 @@ static struct map_desc standard_io_desc[] __initdata = {
},
};
static struct map_desc mmp2_io_desc[] __initdata = {
{
.pfn = __phys_to_pfn(PGU_PHYS_BASE),
.virtual = (unsigned long)PGU_VIRT_BASE,
.length = PGU_PHYS_SIZE,
.type = MT_DEVICE,
},
};
void __init mmp_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
......@@ -44,6 +53,12 @@ void __init mmp_map_io(void)
mmp_chip_id = __raw_readl(MMP_CHIPID);
}
void __init mmp2_map_io(void)
{
mmp_map_io();
iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
}
void mmp_restart(enum reboot_mode mode, const char *cmd)
{
soft_restart(0);
......
......@@ -5,4 +5,5 @@
extern void mmp_timer_init(int irq, unsigned long rate);
extern void __init mmp_map_io(void);
extern void __init mmp2_map_io(void);
extern void mmp_restart(enum reboot_mode, const char *);
......@@ -33,7 +33,7 @@ static const char *const mmp2_dt_board_compat[] __initconst = {
};
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
.map_io = mmp_map_io,
.map_io = mmp2_map_io,
.init_time = mmp_init_time,
.dt_compat = mmp2_dt_board_compat,
MACHINE_END
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