Commit e84957e6 authored by Paul Burton's avatar Paul Burton

MIPS: syscall: Emit Loongson3 sync workarounds within asm

Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had, containing sync & ll instructions respectively.
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
parent 3c1d3f09
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <asm/signal.h> #include <asm/signal.h>
#include <asm/sim.h> #include <asm/sim.h>
#include <asm/shmparam.h> #include <asm/shmparam.h>
#include <asm/sync.h>
#include <asm/sysmips.h> #include <asm/sysmips.h>
#include <asm/switch_to.h> #include <asm/switch_to.h>
...@@ -133,12 +134,12 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) ...@@ -133,12 +134,12 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
[efault] "i" (-EFAULT) [efault] "i" (-EFAULT)
: "memory"); : "memory");
} else if (cpu_has_llsc) { } else if (cpu_has_llsc) {
loongson_llsc_mb();
__asm__ __volatile__ ( __asm__ __volatile__ (
" .set push \n" " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n" " .set "MIPS_ISA_ARCH_LEVEL" \n"
" li %[err], 0 \n" " li %[err], 0 \n"
"1: \n" "1: \n"
" " __SYNC(full, loongson3_war) " \n"
user_ll("%[old]", "(%[addr])") user_ll("%[old]", "(%[addr])")
" move %[tmp], %[new] \n" " move %[tmp], %[new] \n"
"2: \n" "2: \n"
......
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