Commit e898da78 authored by Wanpeng Li's avatar Wanpeng Li Committed by Paolo Bonzini

KVM: LAPIC: Write 0 to TMICT should also cancel vmx-preemption timer

According to the SDM 10.5.4.1:

  A write of 0 to the initial-count register effectively stops the local
  APIC timer, in both one-shot and periodic mode.

However, the lapic timer oneshot/periodic mode which is emulated by vmx-preemption
timer doesn't stop by writing 0 to TMICT since vmx->hv_deadline_tsc is still
programmed and the guest will receive the spurious timer interrupt later. This
patch fixes it by also cancelling the vmx-preemption timer when writing 0 to
the initial-count register.
Reviewed-by: default avatarSean Christopherson <seanjc@google.com>
Signed-off-by: default avatarWanpeng Li <wanpengli@tencent.com>
Message-Id: <1623050385-100988-1-git-send-email-wanpengli@tencent.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 4f13d471
...@@ -1494,6 +1494,15 @@ static void limit_periodic_timer_frequency(struct kvm_lapic *apic) ...@@ -1494,6 +1494,15 @@ static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
static void cancel_hv_timer(struct kvm_lapic *apic); static void cancel_hv_timer(struct kvm_lapic *apic);
static void cancel_apic_timer(struct kvm_lapic *apic)
{
hrtimer_cancel(&apic->lapic_timer.timer);
preempt_disable();
if (apic->lapic_timer.hv_timer_in_use)
cancel_hv_timer(apic);
preempt_enable();
}
static void apic_update_lvtt(struct kvm_lapic *apic) static void apic_update_lvtt(struct kvm_lapic *apic)
{ {
u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
...@@ -1502,11 +1511,7 @@ static void apic_update_lvtt(struct kvm_lapic *apic) ...@@ -1502,11 +1511,7 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
if (apic->lapic_timer.timer_mode != timer_mode) { if (apic->lapic_timer.timer_mode != timer_mode) {
if (apic_lvtt_tscdeadline(apic) != (timer_mode == if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
APIC_LVT_TIMER_TSCDEADLINE)) { APIC_LVT_TIMER_TSCDEADLINE)) {
hrtimer_cancel(&apic->lapic_timer.timer); cancel_apic_timer(apic);
preempt_disable();
if (apic->lapic_timer.hv_timer_in_use)
cancel_hv_timer(apic);
preempt_enable();
kvm_lapic_set_reg(apic, APIC_TMICT, 0); kvm_lapic_set_reg(apic, APIC_TMICT, 0);
apic->lapic_timer.period = 0; apic->lapic_timer.period = 0;
apic->lapic_timer.tscdeadline = 0; apic->lapic_timer.tscdeadline = 0;
...@@ -2092,7 +2097,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) ...@@ -2092,7 +2097,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
if (apic_lvtt_tscdeadline(apic)) if (apic_lvtt_tscdeadline(apic))
break; break;
hrtimer_cancel(&apic->lapic_timer.timer); cancel_apic_timer(apic);
kvm_lapic_set_reg(apic, APIC_TMICT, val); kvm_lapic_set_reg(apic, APIC_TMICT, val);
start_apic_timer(apic); start_apic_timer(apic);
break; break;
......
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