[e1000] 82544 PCI-X hang fix + TSO updates
* Bug fix: 82544 hang with PCI-X: if outgoing Tx buffers terminate within evenly-aligned dwords, and the device is sharing the bus segment with another PCI-X device, 82544 can hang the bus on a split-completion transaction. Fix is to split buffer into two buffers with the first one not terminating within evenly-aligned dword address, and the second one being 4-bytes, which goes as a non-split-conpletion PCI-X transaction. * 8254x controllers that support TSO do an internal calculation to make sure there is enough FIFO space to handle the overhead of each TSO segment before DMA'ing TSO data from host memory. The internal calculation is dependent on the mss of the TSO (defines the number of segments), but the reserved space is a constant, so we need to adjust the maximum size of each buffer queued to the hardware to hold the equation and not overrun the FIFO. This is per TSO because the mss can change from one send to the next.
Showing
Please register or sign in to comment