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Commit eb14b8f5 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
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drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h 

IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR

Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 836bc350
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drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
View file @ eb14b8f5
...@@ -7085,10 +7085,18 @@ ...@@ -7085,10 +7085,18 @@
#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1
#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 #define regCP_GE_MSINVOC_COUNT_HI 0x20a7
#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1
#define regCP_IB1_CMD_BUFSZ 0x20c0
#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1
#define regCP_IB2_CMD_BUFSZ 0x20c1 #define regCP_IB2_CMD_BUFSZ 0x20c1
#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 #define regCP_IB2_CMD_BUFSZ_BASE_IDX 1
#define regCP_ST_CMD_BUFSZ 0x20c2 #define regCP_ST_CMD_BUFSZ 0x20c2
#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 #define regCP_ST_CMD_BUFSZ_BASE_IDX 1
#define regCP_IB1_BASE_LO 0x20cc
#define regCP_IB1_BASE_LO_BASE_IDX 1
#define regCP_IB1_BASE_HI 0x20cd
#define regCP_IB1_BASE_HI_BASE_IDX 1
#define regCP_IB1_BUFSZ 0x20ce
#define regCP_IB1_BUFSZ_BASE_IDX 1
#define regCP_IB2_BASE_LO 0x20cf #define regCP_IB2_BASE_LO 0x20cf
#define regCP_IB2_BASE_LO_BASE_IDX 1 #define regCP_IB2_BASE_LO_BASE_IDX 1
#define regCP_IB2_BASE_HI 0x20d0 #define regCP_IB2_BASE_HI 0x20d0
...@@ -7541,6 +7549,8 @@ ...@@ -7541,6 +7549,8 @@
#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 #define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
#define regCP_MES_DOORBELL_CONTROL6 0x2841 #define regCP_MES_DOORBELL_CONTROL6 0x2841
#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 #define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
#define regCP_MES_GP0_LO 0x2843 #define regCP_MES_GP0_LO 0x2843
#define regCP_MES_GP0_LO_BASE_IDX 1 #define regCP_MES_GP0_LO_BASE_IDX 1
#define regCP_MES_GP0_HI 0x2844 #define regCP_MES_GP0_HI 0x2844
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