Commit eb14ed1a authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Simon Horman

arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29

This patch changes the number of GPIO bank 1 ports to 29 because GP-1-28
port pin of R8A7795 ES2.0 SoC support was added.
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 291e0c49 ("arm64: dts: r8a7795: Add support for R-Car H3 ES2.0")
[geert: Keep 28 GPIOs on H3 ES1.x after r8a7795.dtsi sharing]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent e2767b0f
...@@ -109,6 +109,10 @@ fdp1@fe948000 { ...@@ -109,6 +109,10 @@ fdp1@fe948000 {
}; };
}; };
&gpio1 {
gpio-ranges = <&pfc 0 32 28>;
};
&ipmmu_vi0 { &ipmmu_vi0 {
renesas,ipmmu-main = <&ipmmu_mm 11>; renesas,ipmmu-main = <&ipmmu_mm 11>;
}; };
......
...@@ -240,7 +240,7 @@ gpio1: gpio@e6051000 { ...@@ -240,7 +240,7 @@ gpio1: gpio@e6051000 {
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 32 28>; gpio-ranges = <&pfc 0 32 29>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 911>; clocks = <&cpg CPG_MOD 911>;
......
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