Commit ebae1376 authored by Marcin Wojtas's avatar Marcin Wojtas Committed by David S. Miller

ARM: dts: armada-xp: add buffer manager nodes

Armada XP network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-xp.dtsi - for the actual common BM unit (bm@c0000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c49e99c2
...@@ -253,6 +253,14 @@ crypto@90000 { ...@@ -253,6 +253,14 @@ crypto@90000 {
marvell,crypto-sram-size = <0x800>; marvell,crypto-sram-size = <0x800>;
}; };
bm: bm@c0000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc0000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
xor@f0900 { xor@f0900 {
compatible = "marvell,orion-xor"; compatible = "marvell,orion-xor";
reg = <0xF0900 0x100 reg = <0xF0900 0x100
...@@ -291,6 +299,17 @@ crypto_sram1: sa-sram1 { ...@@ -291,6 +299,17 @@ crypto_sram1: sa-sram1 {
#size-cells = <1>; #size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
}; };
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
}; };
clocks { clocks {
......
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