Commit ec654e50 authored by Stephen Warren's avatar Stephen Warren Committed by Linus Walleij

pinctrl: tegra: support nvidia,io-hv DT property

Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular
pin's IO buffers are configured to accept "high voltage" input signals.
The TRM for different chips names the register field rcv-sel on older
SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl
driver so that DT files can use naming consistent with the TRM.

This new property name will be documented in the patch that adds support
for the new SoC.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Tested-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ea623061
...@@ -103,6 +103,7 @@ static const struct cfg_param { ...@@ -103,6 +103,7 @@ static const struct cfg_param {
{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
{"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
{"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
......
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