Commit ecce87ea authored by Maarten Lankhorst's avatar Maarten Lankhorst Committed by Daniel Vetter

drm/i915: Remove implicitly disabling primary plane for now

Some of the flags that were used are still useful when transitioning
to atomic, so keep those around for now. This removes some of the
complications of crtc->primary_enabled, making it easier to remove.
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent eb3394fa
...@@ -248,12 +248,6 @@ struct intel_plane_state { ...@@ -248,12 +248,6 @@ struct intel_plane_state {
struct drm_rect clip; struct drm_rect clip;
bool visible; bool visible;
/*
* used only for sprite planes to determine when to implicitly
* enable/disable the primary plane
*/
bool hides_primary;
/* /*
* scaler_id * scaler_id
* = -1 : not using a scaler * = -1 : not using a scaler
......
...@@ -166,17 +166,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) ...@@ -166,17 +166,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
pipe_name(pipe), start_vbl_count, end_vbl_count); pipe_name(pipe), start_vbl_count, end_vbl_count);
} }
static void intel_update_primary_plane(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
int reg = DSPCNTR(crtc->plane);
if (crtc->primary_enabled)
I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
else
I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
}
static void static void
skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb, struct drm_framebuffer *fb,
...@@ -438,8 +427,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, ...@@ -438,8 +427,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
} }
intel_update_primary_plane(intel_crtc);
if (key->flags) { if (key->flags) {
I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
...@@ -480,8 +467,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) ...@@ -480,8 +467,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
int plane = intel_plane->plane; int plane = intel_plane->plane;
intel_update_primary_plane(intel_crtc);
I915_WRITE(SPCNTR(pipe, plane), 0); I915_WRITE(SPCNTR(pipe, plane), 0);
/* Activate double buffered register update */ /* Activate double buffered register update */
...@@ -585,8 +570,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, ...@@ -585,8 +570,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
} }
} }
intel_update_primary_plane(intel_crtc);
if (key->flags) { if (key->flags) {
I915_WRITE(SPRKEYVAL(pipe), key->min_value); I915_WRITE(SPRKEYVAL(pipe), key->min_value);
I915_WRITE(SPRKEYMAX(pipe), key->max_value); I915_WRITE(SPRKEYMAX(pipe), key->max_value);
...@@ -629,8 +612,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) ...@@ -629,8 +612,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
intel_update_primary_plane(intel_crtc);
I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
/* Can't leave the scaler enabled... */ /* Can't leave the scaler enabled... */
if (intel_plane->can_scale) if (intel_plane->can_scale)
...@@ -725,8 +706,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, ...@@ -725,8 +706,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
} }
intel_update_primary_plane(intel_crtc);
if (key->flags) { if (key->flags) {
I915_WRITE(DVSKEYVAL(pipe), key->min_value); I915_WRITE(DVSKEYVAL(pipe), key->min_value);
I915_WRITE(DVSKEYMAX(pipe), key->max_value); I915_WRITE(DVSKEYMAX(pipe), key->max_value);
...@@ -764,8 +743,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) ...@@ -764,8 +743,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
intel_update_primary_plane(intel_crtc);
I915_WRITE(DVSCNTR(pipe), 0); I915_WRITE(DVSCNTR(pipe), 0);
/* Disable the scaler */ /* Disable the scaler */
I915_WRITE(DVSSCALE(pipe), 0); I915_WRITE(DVSSCALE(pipe), 0);
...@@ -818,7 +795,7 @@ intel_post_enable_primary(struct drm_crtc *crtc) ...@@ -818,7 +795,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
* @crtc: the CRTC whose primary plane is to be disabled * @crtc: the CRTC whose primary plane is to be disabled
* *
* Performs potentially sleeping operations that must be done before the * Performs potentially sleeping operations that must be done before the
* primary plane is enabled, such as updating FBC and IPS. Note that this may * primary plane is disabled, such as updating FBC and IPS. Note that this may
* be called due to an explicit primary plane update, or due to an implicit * be called due to an explicit primary plane update, or due to an implicit
* disable that is caused when a sprite plane completely hides the primary * disable that is caused when a sprite plane completely hides the primary
* plane. * plane.
...@@ -844,11 +821,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc) ...@@ -844,11 +821,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
hsw_disable_ips(intel_crtc); hsw_disable_ips(intel_crtc);
} }
static bool colorkey_enabled(struct intel_plane *intel_plane)
{
return intel_plane->ckey.flags != I915_SET_COLORKEY_NONE;
}
static int static int
intel_check_sprite_plane(struct drm_plane *plane, intel_check_sprite_plane(struct drm_plane *plane,
struct intel_plane_state *state) struct intel_plane_state *state)
...@@ -1022,23 +994,10 @@ intel_check_sprite_plane(struct drm_plane *plane, ...@@ -1022,23 +994,10 @@ intel_check_sprite_plane(struct drm_plane *plane,
* If the sprite is completely covering the primary plane, * If the sprite is completely covering the primary plane,
* we can disable the primary and save power. * we can disable the primary and save power.
*/ */
state->hides_primary = fb != NULL && drm_rect_equals(dst, clip) &&
!colorkey_enabled(intel_plane);
WARN_ON(state->hides_primary && !state->visible && intel_crtc->active);
if (intel_crtc->active) { if (intel_crtc->active) {
if (intel_crtc->primary_enabled == state->hides_primary)
intel_crtc->atomic.wait_for_flips = true;
if (intel_crtc->primary_enabled && state->hides_primary)
intel_crtc->atomic.pre_disable_primary = true;
intel_crtc->atomic.fb_bits |= intel_crtc->atomic.fb_bits |=
INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe); INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
if (!intel_crtc->primary_enabled && !state->hides_primary)
intel_crtc->atomic.post_enable_primary = true;
if (intel_wm_need_update(plane, &state->base)) if (intel_wm_need_update(plane, &state->base))
intel_crtc->atomic.update_wm = true; intel_crtc->atomic.update_wm = true;
...@@ -1081,8 +1040,6 @@ intel_commit_sprite_plane(struct drm_plane *plane, ...@@ -1081,8 +1040,6 @@ intel_commit_sprite_plane(struct drm_plane *plane,
plane->fb = fb; plane->fb = fb;
if (intel_crtc->active) { if (intel_crtc->active) {
intel_crtc->primary_enabled = !state->hides_primary;
if (state->visible) { if (state->visible) {
crtc_x = state->dst.x1; crtc_x = state->dst.x1;
crtc_y = state->dst.y1; crtc_y = state->dst.y1;
......
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