Commit ed07d82f authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vignesh Raghavendra

arm64: dts: ti: k3-am62p-j722s: Move SoC-specific node properties

Certain device-tree node properties of shared device-tree nodes are
different between the AM62P and J722S SoCs. To avoid overriding the
properties and to avoid redefining the nodes in the k3-{soc}-main.dtsi
having such SoC specific properties, move the properties to the SoC
specific k3-{soc}-main.dtsi files.
Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-9-s-vadapalli@ti.comSigned-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 485705df
......@@ -8,10 +8,8 @@
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x70000000 0x10000>;
};
gic500: interrupt-controller@1800000 {
......@@ -92,7 +90,6 @@ inta_main_dmss: interrupt-controller@48000000 {
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <28>;
ti,interrupt-ranges = <5 69 35>;
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
};
......@@ -539,7 +536,6 @@ main_gpio0: gpio@600000 {
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
......@@ -556,7 +552,6 @@ main_gpio1: gpio@601000 {
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <52>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
......
......@@ -32,3 +32,20 @@ usb1: usb@31100000 {
};
};
};
&oc_sram {
reg = <0x00 0x70000000 0x00 0x10000>;
ranges = <0x00 0x00 0x70000000 0x10000>;
};
&inta_main_dmss {
ti,interrupt-ranges = <5 69 35>;
};
&main_gpio0 {
ti,ngpio = <92>;
};
&main_gpio1 {
ti,ngpio = <52>;
};
......@@ -171,3 +171,20 @@ pcie0_ctrl: pcie0-ctrl@4070 {
reg = <0x4070 0x4>;
};
};
&oc_sram {
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
};
&inta_main_dmss {
ti,interrupt-ranges = <7 71 21>;
};
&main_gpio0 {
ti,ngpio = <87>;
};
&main_gpio1 {
ti,ngpio = <73>;
};
......@@ -232,22 +232,3 @@ cbass_wakeup: bus@b00000 {
/* Include J722S specific peripherals */
#include "k3-j722s-main.dtsi"
/* Main domain overrides */
&inta_main_dmss {
ti,interrupt-ranges = <7 71 21>;
};
&main_gpio0 {
ti,ngpio = <87>;
};
&main_gpio1 {
ti,ngpio = <73>;
};
&oc_sram {
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
};
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