Commit ed6e8103 authored by David S. Miller's avatar David S. Miller

Merge branch 'qed-Enhancements'

Sudarsana Reddy Kalluru says:

====================
qed*: Enhancements.

The patch series adds couple of enhancements to qed/qede drivers.
  - Support for dumping the config id attributes via ethtool -w/W.
  - Support for dumping the GRC data of required memory regions using
    ethtool -w/W interfaces.

Patch (1) adds driver APIs for reading the config id attributes.
Patch (2) adds ethtool support for dumping the config id attributes.
Patch (3) adds support for configuring the GRC dump config flags.
Patch (4) adds ethtool support for dumping the grc dump.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b0274eb0 849dbf09
...@@ -1756,6 +1756,15 @@ static u32 qed_read_unaligned_dword(u8 *buf) ...@@ -1756,6 +1756,15 @@ static u32 qed_read_unaligned_dword(u8 *buf)
return dword; return dword;
} }
/* Sets the value of the specified GRC param */
static void qed_grc_set_param(struct qed_hwfn *p_hwfn,
enum dbg_grc_params grc_param, u32 val)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
dev_data->grc.param_val[grc_param] = val;
}
/* Returns the value of the specified GRC param */ /* Returns the value of the specified GRC param */
static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn, static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn,
enum dbg_grc_params grc_param) enum dbg_grc_params grc_param)
...@@ -5119,6 +5128,69 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn, ...@@ -5119,6 +5128,69 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
return false; return false;
} }
enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
enum dbg_grc_params grc_param, u32 val)
{
enum dbg_status status;
int i;
DP_VERBOSE(p_hwfn, QED_MSG_DEBUG,
"dbg_grc_config: paramId = %d, val = %d\n", grc_param, val);
status = qed_dbg_dev_init(p_hwfn, p_ptt);
if (status != DBG_STATUS_OK)
return status;
/* Initializes the GRC parameters (if not initialized). Needed in order
* to set the default parameter values for the first time.
*/
qed_dbg_grc_init_params(p_hwfn);
if (grc_param >= MAX_DBG_GRC_PARAMS)
return DBG_STATUS_INVALID_ARGS;
if (val < s_grc_param_defs[grc_param].min ||
val > s_grc_param_defs[grc_param].max)
return DBG_STATUS_INVALID_ARGS;
if (s_grc_param_defs[grc_param].is_preset) {
/* Preset param */
/* Disabling a preset is not allowed. Call
* dbg_grc_set_params_default instead.
*/
if (!val)
return DBG_STATUS_INVALID_ARGS;
/* Update all params with the preset values */
for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) {
u32 preset_val;
/* Skip persistent params */
if (s_grc_param_defs[i].is_persistent)
continue;
/* Find preset value */
if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL)
preset_val =
s_grc_param_defs[i].exclude_all_preset_val;
else if (grc_param == DBG_GRC_PARAM_CRASH)
preset_val =
s_grc_param_defs[i].crash_preset_val;
else
return DBG_STATUS_INVALID_ARGS;
qed_grc_set_param(p_hwfn,
(enum dbg_grc_params)i, preset_val);
}
} else {
/* Regular param - set its value */
qed_grc_set_param(p_hwfn, grc_param, val);
}
return DBG_STATUS_OK;
}
/* Assign default GRC param values */ /* Assign default GRC param values */
void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn) void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn)
{ {
...@@ -7997,9 +8069,16 @@ static u32 qed_calc_regdump_header(enum debug_print_features feature, ...@@ -7997,9 +8069,16 @@ static u32 qed_calc_regdump_header(enum debug_print_features feature,
int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
{ {
u8 cur_engine, omit_engine = 0, org_engine; u8 cur_engine, omit_engine = 0, org_engine;
struct qed_hwfn *p_hwfn =
&cdev->hwfns[cdev->dbg_params.engine_for_debug];
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
int grc_params[MAX_DBG_GRC_PARAMS], i;
u32 offset = 0, feature_size; u32 offset = 0, feature_size;
int rc; int rc;
for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
grc_params[i] = dev_data->grc.param_val[i];
if (cdev->num_hwfns == 1) if (cdev->num_hwfns == 1)
omit_engine = 1; omit_engine = 1;
...@@ -8087,6 +8166,9 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) ...@@ -8087,6 +8166,9 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
rc); rc);
} }
for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
dev_data->grc.param_val[i] = grc_params[i];
/* GRC dump - must be last because when mcp stuck it will /* GRC dump - must be last because when mcp stuck it will
* clutter idle_chk, reg_fifo, ... * clutter idle_chk, reg_fifo, ...
*/ */
......
...@@ -3024,6 +3024,21 @@ void qed_read_regs(struct qed_hwfn *p_hwfn, ...@@ -3024,6 +3024,21 @@ void qed_read_regs(struct qed_hwfn *p_hwfn,
*/ */
bool qed_read_fw_info(struct qed_hwfn *p_hwfn, bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, struct fw_info *fw_info); struct qed_ptt *p_ptt, struct fw_info *fw_info);
/**
* @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
*
* @param p_hwfn - HW device data
* @param grc_param - GRC parameter
* @param val - Value to set.
*
* @return error if one of the following holds:
* - the version wasn't set
* - grc_param is invalid
* - val is outside the allowed boundaries
*/
enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
enum dbg_grc_params grc_param, u32 val);
/** /**
* @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
......
...@@ -69,6 +69,8 @@ ...@@ -69,6 +69,8 @@
#define QED_RDMA_SRQS QED_ROCE_QPS #define QED_RDMA_SRQS QED_ROCE_QPS
#define QED_NVM_CFG_SET_FLAGS 0xE #define QED_NVM_CFG_SET_FLAGS 0xE
#define QED_NVM_CFG_SET_PF_FLAGS 0x1E #define QED_NVM_CFG_SET_PF_FLAGS 0x1E
#define QED_NVM_CFG_GET_FLAGS 0xA
#define QED_NVM_CFG_GET_PF_FLAGS 0x1A
static char version[] = static char version[] =
"QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
...@@ -2298,6 +2300,30 @@ static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data) ...@@ -2298,6 +2300,30 @@ static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
return rc; return rc;
} }
static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data,
u32 cmd, u32 entity_id)
{
struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
struct qed_ptt *ptt;
u32 flags, len;
int rc = 0;
ptt = qed_ptt_acquire(hwfn);
if (!ptt)
return -EAGAIN;
DP_VERBOSE(cdev, NETIF_MSG_DRV,
"Read config cmd = %d entity id %d\n", cmd, entity_id);
flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS;
rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len);
if (rc)
DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
qed_ptt_release(hwfn, ptt);
return rc;
}
static int qed_nvm_flash(struct qed_dev *cdev, const char *name) static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
{ {
const struct firmware *image; const struct firmware *image;
...@@ -2557,6 +2583,26 @@ static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf, ...@@ -2557,6 +2583,26 @@ static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
return rc; return rc;
} }
static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val)
{
struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
struct qed_ptt *ptt;
int rc = 0;
if (IS_VF(cdev))
return 0;
ptt = qed_ptt_acquire(hwfn);
if (!ptt)
return -EAGAIN;
rc = qed_dbg_grc_config(hwfn, ptt, cfg_id, val);
qed_ptt_release(hwfn, ptt);
return rc;
}
static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev) static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
{ {
return QED_AFFIN_HWFN_IDX(cdev); return QED_AFFIN_HWFN_IDX(cdev);
...@@ -2610,6 +2656,8 @@ const struct qed_common_ops qed_common_ops_pass = { ...@@ -2610,6 +2656,8 @@ const struct qed_common_ops qed_common_ops_pass = {
.db_recovery_del = &qed_db_recovery_del, .db_recovery_del = &qed_db_recovery_del,
.read_module_eeprom = &qed_read_module_eeprom, .read_module_eeprom = &qed_read_module_eeprom,
.get_affin_hwfn_idx = &qed_get_affin_hwfn_idx, .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
.read_nvm_cfg = &qed_nvm_flash_cfg_read,
.set_grc_config = &qed_set_grc_config,
}; };
void qed_get_protocol_stats(struct qed_dev *cdev, void qed_get_protocol_stats(struct qed_dev *cdev,
......
...@@ -3751,6 +3751,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) ...@@ -3751,6 +3751,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
return 0; return 0;
} }
int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
u32 *p_len)
{
u32 mb_param = 0, resp, param;
int rc;
QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
if (flags & QED_NVM_CFG_OPTION_INIT)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
if (flags & QED_NVM_CFG_OPTION_FREE)
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
QED_MFW_SET_FIELD(mb_param,
DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
entity_id);
}
rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_GET_NVM_CFG_OPTION,
mb_param, &resp, &param, p_len, (u32 *)p_buf);
return rc;
}
int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
u32 len) u32 len)
......
...@@ -1208,6 +1208,21 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); ...@@ -1208,6 +1208,21 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
*/ */
int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
/**
* @brief Get NVM config attribute value.
*
* @param p_hwfn
* @param p_ptt
* @param option_id
* @param entity_id
* @param flags
* @param p_buf
* @param p_len
*/
int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
u32 *p_len);
/** /**
* @brief Set NVM config attribute value. * @brief Set NVM config attribute value.
* *
......
...@@ -177,6 +177,20 @@ enum qede_flags_bit { ...@@ -177,6 +177,20 @@ enum qede_flags_bit {
QEDE_FLAGS_TX_TIMESTAMPING_EN QEDE_FLAGS_TX_TIMESTAMPING_EN
}; };
#define QEDE_DUMP_MAX_ARGS 4
enum qede_dump_cmd {
QEDE_DUMP_CMD_NONE = 0,
QEDE_DUMP_CMD_NVM_CFG,
QEDE_DUMP_CMD_GRCDUMP,
QEDE_DUMP_CMD_MAX
};
struct qede_dump_info {
enum qede_dump_cmd cmd;
u8 num_args;
u32 args[QEDE_DUMP_MAX_ARGS];
};
struct qede_dev { struct qede_dev {
struct qed_dev *cdev; struct qed_dev *cdev;
struct net_device *ndev; struct net_device *ndev;
...@@ -262,6 +276,7 @@ struct qede_dev { ...@@ -262,6 +276,7 @@ struct qede_dev {
struct qede_rdma_dev rdma_info; struct qede_rdma_dev rdma_info;
struct bpf_prog *xdp_prog; struct bpf_prog *xdp_prog;
struct qede_dump_info dump_info;
}; };
enum QEDE_STATE { enum QEDE_STATE {
......
...@@ -48,6 +48,9 @@ ...@@ -48,6 +48,9 @@
{QEDE_RQSTAT_OFFSET(stat_name), QEDE_RQSTAT_STRING(stat_name)} {QEDE_RQSTAT_OFFSET(stat_name), QEDE_RQSTAT_STRING(stat_name)}
#define QEDE_SELFTEST_POLL_COUNT 100 #define QEDE_SELFTEST_POLL_COUNT 100
#define QEDE_DUMP_VERSION 0x1
#define QEDE_DUMP_NVM_BUF_LEN 32
#define QEDE_DUMP_NVM_ARG_COUNT 2
static const struct { static const struct {
u64 offset; u64 offset;
...@@ -1973,6 +1976,114 @@ static int qede_get_module_eeprom(struct net_device *dev, ...@@ -1973,6 +1976,114 @@ static int qede_get_module_eeprom(struct net_device *dev,
return rc; return rc;
} }
static int qede_set_dump(struct net_device *dev, struct ethtool_dump *val)
{
struct qede_dev *edev = netdev_priv(dev);
int rc = 0;
if (edev->dump_info.cmd == QEDE_DUMP_CMD_NONE) {
if (val->flag > QEDE_DUMP_CMD_MAX) {
DP_ERR(edev, "Invalid command %d\n", val->flag);
return -EINVAL;
}
edev->dump_info.cmd = val->flag;
edev->dump_info.num_args = 0;
return 0;
}
if (edev->dump_info.num_args == QEDE_DUMP_MAX_ARGS) {
DP_ERR(edev, "Arg count = %d\n", edev->dump_info.num_args);
return -EINVAL;
}
switch (edev->dump_info.cmd) {
case QEDE_DUMP_CMD_NVM_CFG:
edev->dump_info.args[edev->dump_info.num_args] = val->flag;
edev->dump_info.num_args++;
break;
case QEDE_DUMP_CMD_GRCDUMP:
rc = edev->ops->common->set_grc_config(edev->cdev,
val->flag, 1);
break;
default:
break;
}
return rc;
}
static int qede_get_dump_flag(struct net_device *dev,
struct ethtool_dump *dump)
{
struct qede_dev *edev = netdev_priv(dev);
if (!edev->ops || !edev->ops->common) {
DP_ERR(edev, "Edev ops not populated\n");
return -EINVAL;
}
dump->version = QEDE_DUMP_VERSION;
switch (edev->dump_info.cmd) {
case QEDE_DUMP_CMD_NVM_CFG:
dump->flag = QEDE_DUMP_CMD_NVM_CFG;
dump->len = QEDE_DUMP_NVM_BUF_LEN;
break;
case QEDE_DUMP_CMD_GRCDUMP:
dump->flag = QEDE_DUMP_CMD_GRCDUMP;
dump->len = edev->ops->common->dbg_all_data_size(edev->cdev);
break;
default:
DP_ERR(edev, "Invalid cmd = %d\n", edev->dump_info.cmd);
return -EINVAL;
}
DP_VERBOSE(edev, QED_MSG_DEBUG,
"dump->version = 0x%x dump->flag = %d dump->len = %d\n",
dump->version, dump->flag, dump->len);
return 0;
}
static int qede_get_dump_data(struct net_device *dev,
struct ethtool_dump *dump, void *buf)
{
struct qede_dev *edev = netdev_priv(dev);
int rc = 0;
if (!edev->ops || !edev->ops->common) {
DP_ERR(edev, "Edev ops not populated\n");
edev->dump_info.cmd = QEDE_DUMP_CMD_NONE;
edev->dump_info.num_args = 0;
return -EINVAL;
}
switch (edev->dump_info.cmd) {
case QEDE_DUMP_CMD_NVM_CFG:
if (edev->dump_info.num_args != QEDE_DUMP_NVM_ARG_COUNT) {
DP_ERR(edev, "Arg count = %d required = %d\n",
edev->dump_info.num_args,
QEDE_DUMP_NVM_ARG_COUNT);
return -EINVAL;
}
rc = edev->ops->common->read_nvm_cfg(edev->cdev, (u8 **)&buf,
edev->dump_info.args[0],
edev->dump_info.args[1]);
break;
case QEDE_DUMP_CMD_GRCDUMP:
memset(buf, 0, dump->len);
rc = edev->ops->common->dbg_all_data(edev->cdev, buf);
break;
default:
DP_ERR(edev, "Invalid cmd = %d\n", edev->dump_info.cmd);
rc = -EINVAL;
break;
}
edev->dump_info.cmd = QEDE_DUMP_CMD_NONE;
edev->dump_info.num_args = 0;
return rc;
}
static const struct ethtool_ops qede_ethtool_ops = { static const struct ethtool_ops qede_ethtool_ops = {
.get_link_ksettings = qede_get_link_ksettings, .get_link_ksettings = qede_get_link_ksettings,
.set_link_ksettings = qede_set_link_ksettings, .set_link_ksettings = qede_set_link_ksettings,
...@@ -2014,6 +2125,9 @@ static const struct ethtool_ops qede_ethtool_ops = { ...@@ -2014,6 +2125,9 @@ static const struct ethtool_ops qede_ethtool_ops = {
.get_tunable = qede_get_tunable, .get_tunable = qede_get_tunable,
.set_tunable = qede_set_tunable, .set_tunable = qede_set_tunable,
.flash_device = qede_flash_device, .flash_device = qede_flash_device,
.get_dump_flag = qede_get_dump_flag,
.get_dump_data = qede_get_dump_data,
.set_dump = qede_set_dump,
}; };
static const struct ethtool_ops qede_vf_ethtool_ops = { static const struct ethtool_ops qede_vf_ethtool_ops = {
......
...@@ -1132,6 +1132,26 @@ struct qed_common_ops { ...@@ -1132,6 +1132,26 @@ struct qed_common_ops {
* @param cdev * @param cdev
*/ */
u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev); u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
/**
* @brief read_nvm_cfg - Read NVM config attribute value.
* @param cdev
* @param buf - buffer
* @param cmd - NVM CFG command id
* @param entity_id - Entity id
*
*/
int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
u32 entity_id);
/**
* @brief set_grc_config - Configure value for grc config id.
* @param cdev
* @param cfg_id - grc config id
* @param val - grc config value
*
*/
int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
}; };
#define MASK_FIELD(_name, _value) \ #define MASK_FIELD(_name, _value) \
......
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