ASoC: rsnd: set DIV_EN register on rsnd_adg_set_convert_clk_gen2()

DIV_EN register enable bit is required when you use Gen2 SRC
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

sound/soc/sh/rcar/adg.c

@@ -111,8 +111,8 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
 	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 	struct device *dev = rsnd_priv_to_dev(priv);
-	int idx, sel, div, step;
-	u32 val;
+	int idx, sel, div, step, ret;
+	u32 val, en;
 	unsigned int min, diff;
 	unsigned int sel_rate [] = {
 		clk_get_rate(adg->clk[CLKA]),	/* 0000: CLKA */
@@ -124,6 +124,7 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
 
 	min = ~0;
 	val = 0;
+	en = 0;
 	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 		idx = 0;
 		step = 2;
@@ -136,6 +137,7 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
 			if (min > diff) {
 				val = (sel << 8) | idx;
 				min = diff;
+				en = 1 << (sel + 1); /* fixme */
 			}
 
 			/*
@@ -157,7 +159,15 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
 		return -EIO;
 	}
 
-	return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
+	ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
+	if (ret < 0) {
+		dev_err(dev, "timsel error\n");
+		return ret;
+	}
+
+	rsnd_mod_bset(mod, DIV_EN, en, en);
+
+	return 0;
 }
 
 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,

sound/soc/sh/rcar/gen.c

@@ -253,6 +253,7 @@ static int rsnd_gen2_regmap_init(struct rsnd_priv *priv, struct rsnd_gen *gen)
 		RSND_GEN2_S_REG(gen, ADG,	AUDIO_CLK_SEL0,	0x0c),
 		RSND_GEN2_S_REG(gen, ADG,	AUDIO_CLK_SEL1,	0x10),
 		RSND_GEN2_S_REG(gen, ADG,	AUDIO_CLK_SEL2,	0x14),
+		RSND_GEN2_S_REG(gen, ADG,	DIV_EN,		0x30),
 		RSND_GEN2_S_REG(gen, ADG,	SRCIN_TIMSEL0,	0x34),
 		RSND_GEN2_S_REG(gen, ADG,	SRCIN_TIMSEL1,	0x38),
 		RSND_GEN2_S_REG(gen, ADG,	SRCIN_TIMSEL2,	0x3c),

sound/soc/sh/rcar/rsnd.h

@@ -67,6 +67,7 @@ enum rsnd_reg {
 	RSND_REG_AUDIO_CLK_SEL3,	/* for Gen1 */
 	RSND_REG_AUDIO_CLK_SEL4,	/* for Gen1 */
 	RSND_REG_AUDIO_CLK_SEL5,	/* for Gen1 */
+	RSND_REG_DIV_EN,		/* for Gen2 */
 	RSND_REG_SRCIN_TIMSEL0,		/* for Gen2 */
 	RSND_REG_SRCIN_TIMSEL1,		/* for Gen2 */
 	RSND_REG_SRCIN_TIMSEL2,		/* for Gen2 */