Commit ee6c7507 authored by Tero Kristo's avatar Tero Kristo Committed by Mike Turquette

ARM: dts: dra7 clock data

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 85dc74e9
...@@ -104,6 +104,45 @@ ocp { ...@@ -104,6 +104,45 @@ ocp {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,dra7-cm-core";
reg = <0x4a008000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
counter32k: counter@4ae04000 { counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k"; compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>; reg = <0x4ae04000 0x40>;
...@@ -584,3 +623,5 @@ mcspi4: spi@480ba000 { ...@@ -584,3 +623,5 @@ mcspi4: spi@480ba000 {
}; };
}; };
}; };
/include/ "dra7xx-clocks.dtsi"
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