Commit eef8811d authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by David S. Miller

dt-bindings: net: dwmac-sun8i: Add binding for GMAC on Allwinner R40 SoC

The Allwinner R40 SoC has the EMAC controller supported by dwmac-sun8i.
It is named "GMAC", while EMAC refers to the 10/100 Mbps Ethernet
controller supported by sun4i-emac. The controller is the same, but
the R40 has the glue layer controls in the clock control unit (CCU),
with a reduced RX delay chain, and no TX delay chain.

This patch adds the R40 specific bits to the dwmac-sun8i binding.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a6fe692e
...@@ -7,6 +7,7 @@ Required properties: ...@@ -7,6 +7,7 @@ Required properties:
- compatible: must be one of the following string: - compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac" "allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac" "allwinner,sun8i-h3-emac"
"allwinner,sun8i-r40-gmac"
"allwinner,sun8i-v3s-emac" "allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac" "allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device. - reg: address and length of the register for the device.
...@@ -25,8 +26,10 @@ Required properties: ...@@ -25,8 +26,10 @@ Required properties:
Optional properties: Optional properties:
- allwinner,tx-delay-ps: TX clock delay chain value in ps. - allwinner,tx-delay-ps: TX clock delay chain value in ps.
Range is 0-700. Default is 0. Range is 0-700. Default is 0.
Unavailable for allwinner,sun8i-r40-gmac
- allwinner,rx-delay-ps: RX clock delay chain value in ps. - allwinner,rx-delay-ps: RX clock delay chain value in ps.
Range is 0-3100. Default is 0. Range is 0-3100. Default is 0.
Range is 0-700 for allwinner,sun8i-r40-gmac
Both delay properties need to be a multiple of 100. They control the Both delay properties need to be a multiple of 100. They control the
clock delay for external RGMII PHY. They do not apply to the internal clock delay for external RGMII PHY. They do not apply to the internal
PHY or external non-RGMII PHYs. PHY or external non-RGMII PHYs.
......
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