Commit ef71bb41 authored by Yang Wang's avatar Yang Wang Committed by Alex Deucher

drm/amdgpu: correct mca ipid die/socket/addr decode

correct mca ipid die/socket/addr decode

v2: squash in fix from Yang
Signed-off-by: default avatarYang Wang <kevinyang.wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent efb91fea
...@@ -2392,8 +2392,8 @@ static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT ...@@ -2392,8 +2392,8 @@ static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT
static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info) static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
{ {
uint64_t ipid = entry->regs[MCA_REG_IDX_IPID]; u64 ipid = entry->regs[MCA_REG_IDX_IPID];
uint32_t insthi; u32 instidhi, instid;
/* NOTE: All MCA IPID register share the same format, /* NOTE: All MCA IPID register share the same format,
* so the driver can share the MCMP1 register header file. * so the driver can share the MCMP1 register header file.
...@@ -2402,9 +2402,15 @@ static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_ ...@@ -2402,9 +2402,15 @@ static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_
info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
insthi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi); /*
info->aid = ((insthi >> 2) & 0x03); * Unfied DieID Format: SAASS. A:AID, S:Socket.
info->socket_id = insthi & 0x03; * Unfied DieID[4] = InstanceId[0]
* Unfied DieID[0:3] = InstanceIdHi[0:3]
*/
instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
info->aid = ((instidhi >> 2) & 0x03);
info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
} }
static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
...@@ -2578,6 +2584,7 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct ...@@ -2578,6 +2584,7 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct
uint32_t instlo; uint32_t instlo;
instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo); instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
instlo &= GENMASK(31, 1);
switch (instlo) { switch (instlo) {
case 0x36430400: /* SMNAID XCD 0 */ case 0x36430400: /* SMNAID XCD 0 */
case 0x38430400: /* SMNAID XCD 1 */ case 0x38430400: /* SMNAID XCD 1 */
...@@ -2596,6 +2603,7 @@ static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amd ...@@ -2596,6 +2603,7 @@ static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amd
uint32_t errcode, instlo; uint32_t errcode, instlo;
instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo); instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
instlo &= GENMASK(31, 1);
if (instlo != 0x03b30400) if (instlo != 0x03b30400)
return false; return false;
......
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