Commit efc6b04b authored by Oded Gabbay's avatar Oded Gabbay

habanalabs: update firmware files

Update the firmware headers to the latest version
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 10cab81d
...@@ -542,11 +542,14 @@ enum cpucp_packet_rc { ...@@ -542,11 +542,14 @@ enum cpucp_packet_rc {
*/ */
enum cpucp_temp_type { enum cpucp_temp_type {
cpucp_temp_input, cpucp_temp_input,
cpucp_temp_min = 4,
cpucp_temp_min_hyst,
cpucp_temp_max = 6, cpucp_temp_max = 6,
cpucp_temp_max_hyst, cpucp_temp_max_hyst,
cpucp_temp_crit, cpucp_temp_crit,
cpucp_temp_crit_hyst, cpucp_temp_crit_hyst,
cpucp_temp_offset = 19, cpucp_temp_offset = 19,
cpucp_temp_lowest = 21,
cpucp_temp_highest = 22, cpucp_temp_highest = 22,
cpucp_temp_reset_history = 23 cpucp_temp_reset_history = 23
}; };
...@@ -555,6 +558,7 @@ enum cpucp_in_attributes { ...@@ -555,6 +558,7 @@ enum cpucp_in_attributes {
cpucp_in_input, cpucp_in_input,
cpucp_in_min, cpucp_in_min,
cpucp_in_max, cpucp_in_max,
cpucp_in_lowest = 6,
cpucp_in_highest = 7, cpucp_in_highest = 7,
cpucp_in_reset_history cpucp_in_reset_history
}; };
...@@ -563,6 +567,7 @@ enum cpucp_curr_attributes { ...@@ -563,6 +567,7 @@ enum cpucp_curr_attributes {
cpucp_curr_input, cpucp_curr_input,
cpucp_curr_min, cpucp_curr_min,
cpucp_curr_max, cpucp_curr_max,
cpucp_curr_lowest = 6,
cpucp_curr_highest = 7, cpucp_curr_highest = 7,
cpucp_curr_reset_history cpucp_curr_reset_history
}; };
...@@ -741,6 +746,9 @@ struct cpucp_security_info { ...@@ -741,6 +746,9 @@ struct cpucp_security_info {
* @pll_map: Bit map of supported PLLs for current ASIC version. * @pll_map: Bit map of supported PLLs for current ASIC version.
* @mme_binning_mask: MME binning mask, * @mme_binning_mask: MME binning mask,
* (0 = functional, 1 = binned) * (0 = functional, 1 = binned)
* @dram_binning_mask: DRAM binning mask, 1 bit per dram instance
* (0 = functional 1 = binned)
* @memory_repair_flag: eFuse flag indicating memory repair
*/ */
struct cpucp_info { struct cpucp_info {
struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
...@@ -759,7 +767,9 @@ struct cpucp_info { ...@@ -759,7 +767,9 @@ struct cpucp_info {
__le64 reserved3; __le64 reserved3;
__le64 reserved4; __le64 reserved4;
__u8 reserved5; __u8 reserved5;
__u8 pad[7]; __u8 dram_binning_mask;
__u8 memory_repair_flag;
__u8 pad[5];
struct cpucp_security_info sec_info; struct cpucp_security_info sec_info;
__le32 reserved6; __le32 reserved6;
__u8 pll_map[PLL_MAP_LEN]; __u8 pll_map[PLL_MAP_LEN];
......
...@@ -8,8 +8,6 @@ ...@@ -8,8 +8,6 @@
#ifndef GAUDI_FW_IF_H #ifndef GAUDI_FW_IF_H
#define GAUDI_FW_IF_H #define GAUDI_FW_IF_H
#include <linux/types.h>
#define GAUDI_EVENT_QUEUE_MSI_IDX 8 #define GAUDI_EVENT_QUEUE_MSI_IDX 8
#define GAUDI_NIC_PORT1_MSI_IDX 10 #define GAUDI_NIC_PORT1_MSI_IDX 10
#define GAUDI_NIC_PORT3_MSI_IDX 12 #define GAUDI_NIC_PORT3_MSI_IDX 12
...@@ -78,13 +76,13 @@ struct gaudi_nic_status { ...@@ -78,13 +76,13 @@ struct gaudi_nic_status {
__u32 high_ber_cnt; __u32 high_ber_cnt;
}; };
struct gaudi_flops_2_data { struct gaudi_cold_rst_data {
union { union {
struct { struct {
__u32 spsram_init_done : 1; u32 spsram_init_done : 1;
__u32 reserved : 31; u32 reserved : 31;
}; };
__u32 data; __le32 data;
}; };
}; };
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 #define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 #define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 #define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 #define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
#endif /* GAUDI_REG_MAP_H_ */ #endif /* GAUDI_REG_MAP_H_ */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment