Commit efcc5858 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents dacfa425 a60600fb
......@@ -179,7 +179,7 @@ EXPORT_SYMBOL(rtc_update);
static ssize_t
rtc_read(struct file *file, char *buf, size_t count, loff_t *ppos)
rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
DECLARE_WAITQUEUE(wait, current);
unsigned long data;
......@@ -215,7 +215,7 @@ rtc_read(struct file *file, char *buf, size_t count, loff_t *ppos)
remove_wait_queue(&rtc_wait, &wait);
if (ret == 0) {
ret = put_user(data, (unsigned long *)buf);
ret = put_user(data, (unsigned long __user *)buf);
if (ret == 0)
ret = sizeof(unsigned long);
}
......@@ -241,6 +241,7 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
struct rtc_ops *ops = file->private_data;
struct rtc_time tm;
struct rtc_wkalrm alrm;
void __user *uarg = (void __user *)arg;
int ret = -EINVAL;
switch (cmd) {
......@@ -248,13 +249,13 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
ret = rtc_read_alarm(ops, &alrm);
if (ret)
break;
ret = copy_to_user((void *)arg, &alrm.time, sizeof(tm));
ret = copy_to_user(uarg, &alrm.time, sizeof(tm));
if (ret)
ret = -EFAULT;
break;
case RTC_ALM_SET:
ret = copy_from_user(&alrm.time, (void *)arg, sizeof(tm));
ret = copy_from_user(&alrm.time, uarg, sizeof(tm));
if (ret) {
ret = -EFAULT;
break;
......@@ -272,7 +273,7 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
case RTC_RD_TIME:
rtc_read_time(ops, &tm);
ret = copy_to_user((void *)arg, &tm, sizeof(tm));
ret = copy_to_user(uarg, &tm, sizeof(tm));
if (ret)
ret = -EFAULT;
break;
......@@ -282,11 +283,12 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
ret = -EACCES;
break;
}
ret = copy_from_user(&tm, (void *)arg, sizeof(tm));
if (ret == 0)
ret = rtc_set_time(ops, &tm);
else
ret = copy_from_user(&tm, uarg, sizeof(tm));
if (ret) {
ret = -EFAULT;
break;
}
ret = rtc_set_time(ops, &tm);
break;
case RTC_EPOCH_SET:
......@@ -308,11 +310,11 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
break;
case RTC_EPOCH_READ:
ret = put_user(rtc_epoch, (unsigned long *)arg);
ret = put_user(rtc_epoch, (unsigned long __user *)uarg);
break;
case RTC_WKALM_SET:
ret = copy_from_user(&alrm, (void *)arg, sizeof(alrm));
ret = copy_from_user(&alrm, uarg, sizeof(alrm));
if (ret) {
ret = -EFAULT;
break;
......@@ -324,7 +326,7 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
ret = rtc_read_alarm(ops, &alrm);
if (ret)
break;
ret = copy_to_user((void *)arg, &alrm, sizeof(alrm));
ret = copy_to_user(uarg, &alrm, sizeof(alrm));
if (ret)
ret = -EFAULT;
break;
......@@ -478,7 +480,7 @@ int register_rtc(struct rtc_ops *ops)
ret = misc_register(&rtc_miscdev);
if (ret == 0)
create_proc_read_entry("driver/rtc", 0, 0,
create_proc_read_entry("driver/rtc", 0, NULL,
rtc_read_proc, ops);
}
up(&rtc_sem);
......
......@@ -58,7 +58,7 @@ static inline void wb977_ww(int reg, int val)
outb(reg, 0x370);
outb(val >> 8, 0x371);
outb(reg + 1, 0x370);
outb(val, 0x371);
outb(val & 255, 0x371);
}
#define wb977_device_select(dev) wb977_wb(0x07, dev)
......@@ -488,7 +488,7 @@ static inline void rwa010_waveartist_init(int base, int irq, int dma)
WRITE_RWA(7, 0);
dprintk("WaveArtist base: ");
WRITE_RWA(0x61, base);
WRITE_RWA(0x61, base & 255);
i = inb(0x203);
WRITE_RWA(0x60, base >> 8);
......@@ -510,7 +510,7 @@ static inline void rwa010_soundblaster_init(int sb_base, int al_base, int irq, i
WRITE_RWA(7, 1);
dprintk("SoundBlaster base: ");
WRITE_RWA(0x61, sb_base);
WRITE_RWA(0x61, sb_base & 255);
i = inb(0x203);
WRITE_RWA(0x60, sb_base >> 8);
......@@ -525,7 +525,7 @@ static inline void rwa010_soundblaster_init(int sb_base, int al_base, int irq, i
dprintk("%d (%d)\n", inb(0x203), dma);
dprintk("AdLib base: ");
WRITE_RWA(0x63, al_base);
WRITE_RWA(0x63, al_base & 255);
i = inb(0x203);
WRITE_RWA(0x62, al_base >> 8);
......
......@@ -337,3 +337,8 @@ extern u32 vfp_get_sys(unsigned int reg);
extern void vfp_put_sys(unsigned int reg, u32 val);
u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
/*
* A special flag to tell the normalisation code not to normalise.
*/
#define VFP_NAN_FLAG 0x100
......@@ -195,7 +195,7 @@ u32 vfp_double_normaliseround(int dd, struct vfp_double *vd, u32 fpscr, u32 exce
dd, d, exceptions);
vfp_put_double(dd, d);
}
return exceptions;
return exceptions & ~VFP_NAN_FLAG;
}
/*
......@@ -240,7 +240,7 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn,
/*
* If one was a signalling NAN, raise invalid operation.
*/
return tn == VFP_SNAN || tm == VFP_SNAN ? FPSCR_IOC : 0x100;
return tn == VFP_SNAN || tm == VFP_SNAN ? FPSCR_IOC : VFP_NAN_FLAG;
}
/*
......
......@@ -201,7 +201,7 @@ u32 vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exce
vfp_put_float(sd, d);
}
return exceptions;
return exceptions & ~VFP_NAN_FLAG;
}
/*
......@@ -246,7 +246,7 @@ vfp_propagate_nan(struct vfp_single *vsd, struct vfp_single *vsn,
/*
* If one was a signalling NAN, raise invalid operation.
*/
return tn == VFP_SNAN || tm == VFP_SNAN ? FPSCR_IOC : 0x100;
return tn == VFP_SNAN || tm == VFP_SNAN ? FPSCR_IOC : VFP_NAN_FLAG;
}
......
......@@ -653,6 +653,7 @@ static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
static void pxafb_setup_gpio(struct pxafb_info *fbi)
{
int gpio, ldd_bits;
unsigned int lccr0 = fbi->lccr0;
/*
......@@ -663,49 +664,31 @@ static void pxafb_setup_gpio(struct pxafb_info *fbi)
if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
(lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
(lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
{
// bits 58-61
GPDR1 |= (0xf << 26);
GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
// bits 74-77
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
}
ldd_bits = 4;
/* 8 bit interface */
else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
((lccr0 & LCCR0_CMS) == LCCR0_Color &&
(lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
{
// bits 58-65
GPDR1 |= (0x3f << 26);
GPDR2 |= (0x3);
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
// bits 74-77
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
}
ldd_bits = 8;
/* 16 bit interface */
else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
{
// bits 58-77
GPDR1 |= (0x3f << 26);
GPDR2 |= 0x00003fff;
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
}
ldd_bits = 16;
else {
printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
return;
}
for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
}
static void pxafb_enable_controller(struct pxafb_info *fbi)
......
......@@ -143,6 +143,7 @@ typedef struct { /* Card handler routines */
#define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
#define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
(ec)->resource[nr].start + 1)
#define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
/*
* This contains all the info needed on an expansion card
......
......@@ -97,23 +97,6 @@ void __set_irq_handler(unsigned int irq, irq_handler_t, int);
void set_irq_chip(unsigned int irq, struct irqchip *);
void set_irq_flags(unsigned int irq, unsigned int flags);
#ifdef not_yet
/*
* This is to be used by the top-level machine IRQ decoder only.
*/
static inline void call_irq(struct pt_regs *regs, unsigned int irq)
{
struct irqdesc *desc = irq_desc + irq;
spin_lock(&irq_controller_lock);
desc->handle(irq, desc, regs);
spin_unlock(&irq_controller_lock);
if (softirq_pending(smp_processor_id()))
do_softirq();
}
#endif
#define IRQF_VALID (1 << 0)
#define IRQF_PROBE (1 << 1)
#define IRQF_NOAUTOEN (1 << 2)
......
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