Commit f07ab7a0 authored by Andreas Färber's avatar Andreas Färber Committed by Michal Simek

ARM: dts: zynq: Add SPI

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
Reviewed-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent fbb4add8
......@@ -140,6 +140,30 @@ uart1: serial@e0001000 {
interrupts = <0 50 4>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
......
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