Commit f0fea981 authored by Jani Nikula's avatar Jani Nikula

drm/i915: pass dev_priv explicitly to DSPARB

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPARB register macro.
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9e8dc8978ce3122a0e9c53778be547875a9ae6d8.1717514638.git.jani.nikula@intel.comSigned-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 58d18ae5
...@@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) ...@@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
switch (pipe) { switch (pipe) {
case PIPE_A: case PIPE_A:
dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); dsparb = intel_uncore_read(&dev_priv->uncore,
DSPARB(dev_priv));
dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
break; break;
case PIPE_B: case PIPE_B:
dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); dsparb = intel_uncore_read(&dev_priv->uncore,
DSPARB(dev_priv));
dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
...@@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) ...@@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane) enum i9xx_plane_id i9xx_plane)
{ {
u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size; int size;
size = dsparb & 0x7f; size = dsparb & 0x7f;
...@@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, ...@@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
static int i830_get_fifo_size(struct drm_i915_private *dev_priv, static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane) enum i9xx_plane_id i9xx_plane)
{ {
u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size; int size;
size = dsparb & 0x1ff; size = dsparb & 0x1ff;
...@@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv, ...@@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
static int i845_get_fifo_size(struct drm_i915_private *dev_priv, static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane) enum i9xx_plane_id i9xx_plane)
{ {
u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
int size; int size;
size = dsparb & 0x7f; size = dsparb & 0x7f;
...@@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, ...@@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
switch (crtc->pipe) { switch (crtc->pipe) {
case PIPE_A: case PIPE_A:
dsparb = intel_uncore_read_fw(uncore, DSPARB); dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
dsparb2 = intel_uncore_read_fw(uncore, DSPARB2); dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
...@@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, ...@@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
intel_uncore_write_fw(uncore, DSPARB, dsparb); intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
intel_uncore_write_fw(uncore, DSPARB2, dsparb2); intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
break; break;
case PIPE_B: case PIPE_B:
dsparb = intel_uncore_read_fw(uncore, DSPARB); dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
dsparb2 = intel_uncore_read_fw(uncore, DSPARB2); dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
...@@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, ...@@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
intel_uncore_write_fw(uncore, DSPARB, dsparb); intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
intel_uncore_write_fw(uncore, DSPARB2, dsparb2); intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
break; break;
case PIPE_C: case PIPE_C:
...@@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, ...@@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
break; break;
} }
intel_uncore_posting_read_fw(uncore, DSPARB); intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
spin_unlock(&uncore->lock); spin_unlock(&uncore->lock);
} }
......
...@@ -1903,7 +1903,7 @@ ...@@ -1903,7 +1903,7 @@
#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
#define PLANEA_INVALID_GTT_STATUS REG_BIT(0) #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
#define DSPARB_CSTART_MASK (0x7f << 7) #define DSPARB_CSTART_MASK (0x7f << 7)
#define DSPARB_CSTART_SHIFT 7 #define DSPARB_CSTART_SHIFT 7
#define DSPARB_BSTART_MASK (0x7f) #define DSPARB_BSTART_MASK (0x7f)
......
...@@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv) ...@@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv)
/* Display arbitration control */ /* Display arbitration control */
if (GRAPHICS_VER(dev_priv) <= 4) if (GRAPHICS_VER(dev_priv) <= 4)
dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
DSPARB(dev_priv));
if (GRAPHICS_VER(dev_priv) == 4) if (GRAPHICS_VER(dev_priv) == 4)
pci_read_config_word(pdev, GCDGMBUS, pci_read_config_word(pdev, GCDGMBUS,
...@@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv) ...@@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
/* Display arbitration */ /* Display arbitration */
if (GRAPHICS_VER(dev_priv) <= 4) if (GRAPHICS_VER(dev_priv) <= 4)
intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB); intel_de_write(dev_priv, DSPARB(dev_priv),
dev_priv->regfile.saveDSPARB);
intel_vga_redisable(dev_priv); intel_vga_redisable(dev_priv);
......
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