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Commit f1c9c979 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 's5p-fixes-for-linus' of... 

Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410
  ARM: S3C64XX: Fix coding style errors on mach-real6410
  ARM: S3C64XX: Prototype SPI devices
  ARM: S3C64XX: Fix dev-spi build
  ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr
  ARM: SAMSUNG: Fix on drive strength value
  ARM: S5PV210: Add FIMC clocks
  ARM: S5PV210: Reduce the iodesc length of systimer
  ARM: S5PV210: Update I2C-1 Clock Register Property.
  ARM: S5P: Decrease IO Registers memory region size on FIMC
  ARM: S5P: Fix DMA coherent mask for FIMC
parents 112d421d 4d89ecaa
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arch/arm/mach-s3c64xx/dev-spi.c
View file @ f1c9c979
...@@ -18,10 +18,11 @@ ...@@ -18,10 +18,11 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/gpio-bank-c.h> #include <mach/gpio-bank-c.h>
#include <mach/spi-clocks.h> #include <mach/spi-clocks.h>
#include <mach/irqs.h>
#include <plat/s3c64xx-spi.h> #include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/irqs.h> #include <plat/devs.h>
static char *spi_src_clks[] = { static char *spi_src_clks[] = {
[S3C64XX_SPI_SRCCLK_PCLK] = "pclk", [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
......
arch/arm/mach-s3c64xx/mach-real6410.c
View file @ f1c9c979
...@@ -30,73 +30,73 @@ ...@@ -30,73 +30,73 @@
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = UCON, .ucon = UCON,
.ulcon = ULCON, .ulcon = ULCON,
.ufcon = UFCON, .ufcon = UFCON,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = UCON, .ucon = UCON,
.ulcon = ULCON, .ulcon = ULCON,
.ufcon = UFCON, .ufcon = UFCON,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = UCON, .ucon = UCON,
.ulcon = ULCON, .ulcon = ULCON,
.ufcon = UFCON, .ufcon = UFCON,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = UCON, .ucon = UCON,
.ulcon = ULCON, .ulcon = ULCON,
.ufcon = UFCON, .ufcon = UFCON,
}, },
}; };
/* DM9000AEP 10/100 ethernet controller */ /* DM9000AEP 10/100 ethernet controller */
static struct resource real6410_dm9k_resource[] = { static struct resource real6410_dm9k_resource[] = {
[0] = { [0] = {
.start = S3C64XX_PA_XM0CSN1, .start = S3C64XX_PA_XM0CSN1,
.end = S3C64XX_PA_XM0CSN1 + 1, .end = S3C64XX_PA_XM0CSN1 + 1,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM
}, },
[1] = { [1] = {
.start = S3C64XX_PA_XM0CSN1 + 4, .start = S3C64XX_PA_XM0CSN1 + 4,
.end = S3C64XX_PA_XM0CSN1 + 5, .end = S3C64XX_PA_XM0CSN1 + 5,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM
}, },
[2] = { [2] = {
.start = S3C_EINT(7), .start = S3C_EINT(7),
.end = S3C_EINT(7), .end = S3C_EINT(7),
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
} }
}; };
static struct dm9000_plat_data real6410_dm9k_pdata = { static struct dm9000_plat_data real6410_dm9k_pdata = {
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
}; };
static struct platform_device real6410_device_eth = { static struct platform_device real6410_device_eth = {
.name = "dm9000", .name = "dm9000",
.id = -1, .id = -1,
.num_resources = ARRAY_SIZE(real6410_dm9k_resource), .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
.resource = real6410_dm9k_resource, .resource = real6410_dm9k_resource,
.dev = { .dev = {
.platform_data = &real6410_dm9k_pdata, .platform_data = &real6410_dm9k_pdata,
}, },
}; };
static struct platform_device *real6410_devices[] __initdata = { static struct platform_device *real6410_devices[] __initdata = {
...@@ -129,12 +129,12 @@ static void __init real6410_machine_init(void) ...@@ -129,12 +129,12 @@ static void __init real6410_machine_init(void)
/* set timing for nCS1 suitable for ethernet chip */ /* set timing for nCS1 suitable for ethernet chip */
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) | (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
(13 << S3C64XX_SROM_BCX__TACC__SHIFT) | (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
} }
......
arch/arm/mach-s5pv210/clock.c
View file @ f1c9c979
...@@ -280,6 +280,24 @@ static struct clk init_clocks_disable[] = { ...@@ -280,6 +280,24 @@ static struct clk init_clocks_disable[] = {
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29), .ctrlbit = (1<<29),
}, {
.name = "fimc",
.id = 0,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "fimc",
.id = 1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "fimc",
.id = 2,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26),
}, { }, {
.name = "otg", .name = "otg",
.id = -1, .id = -1,
...@@ -357,7 +375,7 @@ static struct clk init_clocks_disable[] = { ...@@ -357,7 +375,7 @@ static struct clk init_clocks_disable[] = {
.id = 1, .id = 1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<8), .ctrlbit = (1 << 10),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 2, .id = 2,
......
arch/arm/mach-s5pv210/cpu.c
View file @ f1c9c979
...@@ -47,7 +47,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = { ...@@ -47,7 +47,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
{ {
.virtual = (unsigned long)S5P_VA_SYSTIMER, .virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
.length = SZ_1M, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)VA_VIC2, .virtual = (unsigned long)VA_VIC2,
......
arch/arm/plat-s5p/dev-fimc0.c
View file @ f1c9c979
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h> #include <linux/ioport.h>
...@@ -18,7 +19,7 @@ ...@@ -18,7 +19,7 @@
static struct resource s5p_fimc0_resource[] = { static struct resource s5p_fimc0_resource[] = {
[0] = { [0] = {
.start = S5P_PA_FIMC0, .start = S5P_PA_FIMC0,
.end = S5P_PA_FIMC0 + SZ_1M - 1, .end = S5P_PA_FIMC0 + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -28,9 +29,15 @@ static struct resource s5p_fimc0_resource[] = { ...@@ -28,9 +29,15 @@ static struct resource s5p_fimc0_resource[] = {
}, },
}; };
static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32);
struct platform_device s5p_device_fimc0 = { struct platform_device s5p_device_fimc0 = {
.name = "s5p-fimc", .name = "s5p-fimc",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(s5p_fimc0_resource), .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
.resource = s5p_fimc0_resource, .resource = s5p_fimc0_resource,
.dev = {
.dma_mask = &s5p_fimc0_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
}; };
arch/arm/plat-s5p/dev-fimc1.c
View file @ f1c9c979
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h> #include <linux/ioport.h>
...@@ -18,7 +19,7 @@ ...@@ -18,7 +19,7 @@
static struct resource s5p_fimc1_resource[] = { static struct resource s5p_fimc1_resource[] = {
[0] = { [0] = {
.start = S5P_PA_FIMC1, .start = S5P_PA_FIMC1,
.end = S5P_PA_FIMC1 + SZ_1M - 1, .end = S5P_PA_FIMC1 + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -28,9 +29,15 @@ static struct resource s5p_fimc1_resource[] = { ...@@ -28,9 +29,15 @@ static struct resource s5p_fimc1_resource[] = {
}, },
}; };
static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32);
struct platform_device s5p_device_fimc1 = { struct platform_device s5p_device_fimc1 = {
.name = "s5p-fimc", .name = "s5p-fimc",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(s5p_fimc1_resource), .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
.resource = s5p_fimc1_resource, .resource = s5p_fimc1_resource,
.dev = {
.dma_mask = &s5p_fimc1_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
}; };
arch/arm/plat-s5p/dev-fimc2.c
View file @ f1c9c979
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h> #include <linux/ioport.h>
...@@ -18,7 +19,7 @@ ...@@ -18,7 +19,7 @@
static struct resource s5p_fimc2_resource[] = { static struct resource s5p_fimc2_resource[] = {
[0] = { [0] = {
.start = S5P_PA_FIMC2, .start = S5P_PA_FIMC2,
.end = S5P_PA_FIMC2 + SZ_1M - 1, .end = S5P_PA_FIMC2 + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -28,9 +29,15 @@ static struct resource s5p_fimc2_resource[] = { ...@@ -28,9 +29,15 @@ static struct resource s5p_fimc2_resource[] = {
}, },
}; };
static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32);
struct platform_device s5p_device_fimc2 = { struct platform_device s5p_device_fimc2 = {
.name = "s5p-fimc", .name = "s5p-fimc",
.id = 2, .id = 2,
.num_resources = ARRAY_SIZE(s5p_fimc2_resource), .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
.resource = s5p_fimc2_resource, .resource = s5p_fimc2_resource,
.dev = {
.dma_mask = &s5p_fimc2_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
}; };
arch/arm/plat-samsung/gpio-config.c
View file @ f1c9c979
...@@ -273,13 +273,13 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) ...@@ -273,13 +273,13 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
if (!chip) if (!chip)
return -EINVAL; return -EINVAL;
off = chip->chip.base - pin; off = pin - chip->chip.base;
shift = off * 2; shift = off * 2;
reg = chip->base + 0x0C; reg = chip->base + 0x0C;
drvstr = __raw_readl(reg); drvstr = __raw_readl(reg);
drvstr = 0xffff & (0x3 << shift);
drvstr = drvstr >> shift; drvstr = drvstr >> shift;
drvstr &= 0x3;
return (__force s5p_gpio_drvstr_t)drvstr; return (__force s5p_gpio_drvstr_t)drvstr;
} }
...@@ -296,11 +296,12 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) ...@@ -296,11 +296,12 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
if (!chip) if (!chip)
return -EINVAL; return -EINVAL;
off = chip->chip.base - pin; off = pin - chip->chip.base;
shift = off * 2; shift = off * 2;
reg = chip->base + 0x0C; reg = chip->base + 0x0C;
tmp = __raw_readl(reg); tmp = __raw_readl(reg);
tmp &= ~(0x3 << shift);
tmp |= drvstr << shift; tmp |= drvstr << shift;
__raw_writel(tmp, reg); __raw_writel(tmp, reg);
......
arch/arm/plat-samsung/include/plat/gpio-cfg.h
View file @ f1c9c979
...@@ -143,12 +143,12 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); ...@@ -143,12 +143,12 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
/* Define values for the drvstr available for each gpio pin. /* Define values for the drvstr available for each gpio pin.
* *
* These values control the value of the output signal driver strength, * These values control the value of the output signal driver strength,
* configurable on most pins on the S5C series. * configurable on most pins on the S5P series.
*/ */
#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x00) #define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x01) #define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x10) #define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x11) #define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
/** /**
* s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
......
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