Commit f222a1ba authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd

clk: mediatek: mt6795: Add support for frequency hopping through FHCTL

Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-5-angelogioacchino.delregno@collabora.comReviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 4ba8590f
......@@ -7,8 +7,10 @@
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#define REG_REF2USB 0x8
#define REG_AP_PLL_CON7 0x1c
......@@ -58,6 +60,56 @@ static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
};
enum fh_pll_id {
FH_CA53PLL_LL,
FH_CA53PLL_BL,
FH_MAINPLL,
FH_MPLL,
FH_MSDCPLL,
FH_MMPLL,
FH_VENCPLL,
FH_TVDPLL,
FH_VCODECPLL,
FH_NR_FH,
};
#define _FH(_pllid, _fhid, _slope, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fh_ver = FHCTL_PLLFH_V1, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = _slope, \
.slope1_value = _slope, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset)
#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset)
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
};
static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
{
void __iomem *reg = base + REG_AP_PLL_CON7;
......@@ -85,6 +137,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
struct clk_hw_onecell_data *clk_data;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
const u8 *fhctl_node = "mediatek,mt6795-fhctl";
void __iomem *base;
struct clk_hw *hw;
int ret;
......@@ -97,7 +150,9 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;
......@@ -124,7 +179,8 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
unregister_ref2usb:
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
......@@ -137,7 +193,8 @@ static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
of_clk_del_provider(node);
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
return 0;
......
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