Commit f24d991b authored by John Clements's avatar John Clements Committed by Alex Deucher

drm/amdgpu: Update RAS XGMI Error Query

Resolve bug querying error on unsupported ASIC
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarJohn Clements <john.clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3907c492
...@@ -848,7 +848,6 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, ...@@ -848,7 +848,6 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
} }
break; break;
case CHIP_VEGA20: case CHIP_VEGA20:
default:
/* check xgmi pcs error */ /* check xgmi pcs error */
for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
...@@ -864,6 +863,9 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, ...@@ -864,6 +863,9 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
data, &ue_cnt, &ce_cnt, false); data, &ue_cnt, &ce_cnt, false);
} }
break; break;
default:
dev_warn(adev->dev, "XGMI RAS error query not supported");
break;
} }
adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
......
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