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Commit f2b7e3c5 authored by Kukjin Kim's avatar Kukjin Kim
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Merge branch 'next-s5p' into for-next 

Conflicts:
	arch/arm/mach-s5pv210/mach-aquila.c
	arch/arm/mach-s5pv210/mach-goni.c
parents 6b8eda04 0fdb480e
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Showing with 202 additions and 129 deletions
arch/arm/mach-s5p6440/include/mach/irqs.h
View file @ f2b7e3c5
...@@ -51,7 +51,7 @@ ...@@ -51,7 +51,7 @@
#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) #define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
#define IRQ_FIMGVG S5P_IRQ_VIC1(20) #define IRQ_FIMGVG S5P_IRQ_VIC1(20)
#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
#define IRQ_PMUIRQ S5P_IRQ_VIC1(23) #define IRQ_PMU S5P_IRQ_VIC1(23)
#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) #define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) #define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
......
arch/arm/mach-s5p6440/include/mach/system.h
View file @ f2b7e3c5
...@@ -13,12 +13,9 @@ ...@@ -13,12 +13,9 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__ #define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void) #include <plat/system-reset.h>
{
/* nothing here yet */
}
static void arch_reset(char mode, const char *cmd) static void arch_idle(void)
{ {
/* nothing here yet */ /* nothing here yet */
} }
......
arch/arm/mach-s5p6440/mach-smdk6440.c
View file @ f2b7e3c5
...@@ -43,16 +43,16 @@ ...@@ -43,16 +43,16 @@
#include <plat/adc.h> #include <plat/adc.h>
#include <plat/ts.h> #include <plat/ts.h>
#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 #define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ #define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_TXTRIG16 | \ S3C2440_UFCON_TXTRIG16 | \
S3C2410_UFCON_RXTRIG8) S3C2410_UFCON_RXTRIG8)
...@@ -60,30 +60,30 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { ...@@ -60,30 +60,30 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5P6440_UCON_DEFAULT, .ucon = SMDK6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT, .ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT, .ufcon = SMDK6440_UFCON_DEFAULT,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5P6440_UCON_DEFAULT, .ucon = SMDK6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT, .ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT, .ufcon = SMDK6440_UFCON_DEFAULT,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5P6440_UCON_DEFAULT, .ucon = SMDK6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT, .ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT, .ufcon = SMDK6440_UFCON_DEFAULT,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5P6440_UCON_DEFAULT, .ucon = SMDK6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT, .ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT, .ufcon = SMDK6440_UFCON_DEFAULT,
}, },
}; };
......
arch/arm/mach-s5p6442/include/mach/irqs.h
View file @ f2b7e3c5
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define IRQ_GPIOINT S5P_IRQ_VIC0(30) #define IRQ_GPIOINT S5P_IRQ_VIC0(30)
/* VIC1 */ /* VIC1 */
#define IRQ_nPMUIRQ S5P_IRQ_VIC1(0) #define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_ONENAND S5P_IRQ_VIC1(7)
#define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART0 S5P_IRQ_VIC1(10)
#define IRQ_UART1 S5P_IRQ_VIC1(11) #define IRQ_UART1 S5P_IRQ_VIC1(11)
......
arch/arm/mach-s5p6442/include/mach/system.h
View file @ f2b7e3c5
...@@ -13,12 +13,9 @@ ...@@ -13,12 +13,9 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__ #define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void) #include <plat/system-reset.h>
{
/* nothing here yet */
}
static void arch_reset(char mode, const char *cmd) static void arch_idle(void)
{ {
/* nothing here yet */ /* nothing here yet */
} }
......
arch/arm/mach-s5p6442/mach-smdk6442.c
View file @ f2b7e3c5
...@@ -27,16 +27,16 @@ ...@@ -27,16 +27,16 @@
#include <plat/cpu.h> #include <plat/cpu.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 #define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ #define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4) S5PV210_UFCON_RXTRIG4)
...@@ -44,23 +44,23 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { ...@@ -44,23 +44,23 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5P6442_UCON_DEFAULT, .ucon = SMDK6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT, .ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT, .ufcon = SMDK6442_UFCON_DEFAULT,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5P6442_UCON_DEFAULT, .ucon = SMDK6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT, .ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT, .ufcon = SMDK6442_UFCON_DEFAULT,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5P6442_UCON_DEFAULT, .ucon = SMDK6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT, .ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT, .ufcon = SMDK6442_UFCON_DEFAULT,
}, },
}; };
......
arch/arm/mach-s5pc100/include/mach/irqs.h
View file @ f2b7e3c5
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#define IRQ_GPIOINT S5P_IRQ_VIC0(30) #define IRQ_GPIOINT S5P_IRQ_VIC0(30)
/* VIC1: ARM, power, memory, connectivity */ /* VIC1: ARM, power, memory, connectivity */
#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) #define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
......
arch/arm/mach-s5pc100/include/mach/system.h
View file @ f2b7e3c5
...@@ -11,18 +11,11 @@ ...@@ -11,18 +11,11 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__ #define __ASM_ARCH_SYSTEM_H __FILE__
#include <linux/io.h> #include <plat/system-reset.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
static void arch_idle(void) static void arch_idle(void)
{ {
/* nothing here yet */ /* nothing here yet */
} }
static void arch_reset(char mode, const char *cmd)
{
__raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
return;
}
#endif /* __ASM_ARCH_IRQ_H */ #endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s5pc100/mach-smdkc100.c
View file @ f2b7e3c5
...@@ -49,16 +49,16 @@ ...@@ -49,16 +49,16 @@
#include <plat/ts.h> #include <plat/ts.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 #define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ #define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_RXTRIG8 | \ S3C2440_UFCON_RXTRIG8 | \
S3C2440_UFCON_TXTRIG16) S3C2440_UFCON_TXTRIG16)
...@@ -66,30 +66,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { ...@@ -66,30 +66,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5PC100_UCON_DEFAULT, .ucon = SMDKC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT, .ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT, .ufcon = SMDKC100_UFCON_DEFAULT,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5PC100_UCON_DEFAULT, .ucon = SMDKC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT, .ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT, .ufcon = SMDKC100_UFCON_DEFAULT,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5PC100_UCON_DEFAULT, .ucon = SMDKC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT, .ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT, .ufcon = SMDKC100_UFCON_DEFAULT,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5PC100_UCON_DEFAULT, .ucon = SMDKC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT, .ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT, .ufcon = SMDKC100_UFCON_DEFAULT,
}, },
}; };
......
arch/arm/mach-s5pv210/include/mach/irqs.h
View file @ f2b7e3c5
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
/* VIC1: ARM, Power, Memory, Connectivity, Storage */ /* VIC1: ARM, Power, Memory, Connectivity, Storage */
#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) #define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
......
arch/arm/mach-s5pv210/include/mach/system.h
View file @ f2b7e3c5
...@@ -13,12 +13,9 @@ ...@@ -13,12 +13,9 @@
#ifndef __ASM_ARCH_SYSTEM_H #ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__ #define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void) #include <plat/system-reset.h>
{
/* nothing here yet */
}
static void arch_reset(char mode, const char *cmd) static void arch_idle(void)
{ {
/* nothing here yet */ /* nothing here yet */
} }
......
arch/arm/mach-s5pv210/mach-aquila.c
View file @ f2b7e3c5
...@@ -38,52 +38,52 @@ ...@@ -38,52 +38,52 @@
#include <plat/sdhci.h> #include <plat/sdhci.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 #define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE #define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = AQUILA_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = AQUILA_ULCON_DEFAULT,
/* /*
* Actually UART0 can support 256 bytes fifo, but aquila board * Actually UART0 can support 256 bytes fifo, but aquila board
* supports 128 bytes fifo because of initial chip bug * supports 128 bytes fifo because of initial chip bug
*/ */
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = AQUILA_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = AQUILA_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = AQUILA_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
}, },
}; };
......
arch/arm/mach-s5pv210/mach-goni.c
View file @ f2b7e3c5
...@@ -38,48 +38,48 @@ ...@@ -38,48 +38,48 @@
#include <plat/sdhci.h> #include <plat/sdhci.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 #define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE #define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = GONI_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = GONI_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = GONI_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = GONI_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = GONI_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = GONI_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = GONI_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = GONI_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT | .ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
}, },
}; };
......
arch/arm/mach-s5pv210/mach-smdkc110.c
View file @ f2b7e3c5
...@@ -30,16 +30,16 @@ ...@@ -30,16 +30,16 @@
#include <plat/iic.h> #include <plat/iic.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 #define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ #define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4) S5PV210_UFCON_RXTRIG4)
...@@ -47,30 +47,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { ...@@ -47,30 +47,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKC110_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKC110_UFCON_DEFAULT,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKC110_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKC110_UFCON_DEFAULT,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKC110_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKC110_UFCON_DEFAULT,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKC110_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKC110_UFCON_DEFAULT,
}, },
}; };
......
arch/arm/mach-s5pv210/mach-smdkv210.c
View file @ f2b7e3c5
...@@ -33,16 +33,16 @@ ...@@ -33,16 +33,16 @@
#include <plat/keypad.h> #include <plat/keypad.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */ /* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \ S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN) S3C2443_UCON_RXERR_IRQEN)
#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 #define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ #define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4) S5PV210_UFCON_RXTRIG4)
...@@ -50,30 +50,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { ...@@ -50,30 +50,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKV210_UFCON_DEFAULT,
}, },
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKV210_UFCON_DEFAULT,
}, },
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKV210_UFCON_DEFAULT,
}, },
[3] = { [3] = {
.hwport = 3, .hwport = 3,
.flags = 0, .flags = 0,
.ucon = S5PV210_UCON_DEFAULT, .ucon = SMDKV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT, .ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT, .ufcon = SMDKV210_UFCON_DEFAULT,
}, },
}; };
......
arch/arm/plat-s5p/Makefile
View file @ f2b7e3c5
...@@ -12,6 +12,7 @@ obj- := ...@@ -12,6 +12,7 @@ obj- :=
# Core files # Core files
obj-y += dev-pmu.o
obj-y += dev-uart.o obj-y += dev-uart.o
obj-y += cpu.o obj-y += cpu.o
obj-y += clock.o obj-y += clock.o
......
arch/arm/plat-s5p/cpu.c
View file @ f2b7e3c5
...@@ -115,6 +115,11 @@ static struct map_desc s5p_iodesc[] __initdata = { ...@@ -115,6 +115,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5P_PA_GPIO), .pfn = __phys_to_pfn(S5P_PA_GPIO),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(S3C_PA_WDT),
.length = SZ_4K,
.type = MT_DEVICE,
}, },
}; };
......
arch/arm/plat-s5p/dev-pmu.c 0 → 100644
View file @ f2b7e3c5
/*
* linux/arch/arm/plat-s5p/dev-pmu.c
*
* Copyright (C) 2010 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/platform_device.h>
#include <asm/pmu.h>
#include <mach/irqs.h>
static struct resource s5p_pmu_resource = {
.start = IRQ_PMU,
.end = IRQ_PMU,
.flags = IORESOURCE_IRQ,
};
struct platform_device s5p_device_pmu = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
.resource = &s5p_pmu_resource,
};
static int __init s5p_pmu_init(void)
{
platform_device_register(&s5p_device_pmu);
return 0;
}
arch_initcall(s5p_pmu_init);
arch/arm/plat-s5p/include/plat/reset.h 0 → 100644
View file @ f2b7e3c5
/* linux/arch/arm/plat-s5p/include/plat/reset.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_S5P_RESET_H
#define __ASM_PLAT_S5P_RESET_H __FILE__
extern void (*s5p_reset_hook)(void);
#endif /* __ASM_PLAT_S5P_RESET_H */
arch/arm/plat-s5p/include/plat/system-reset.h 0 → 100644
View file @ f2b7e3c5
/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
*
* S5P - System define for arch_reset()
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/watchdog-reset.h>
void (*s5p_reset_hook)(void);
static void arch_reset(char mode, const char *cmd)
{
/* SWRESET support in s5p_reset_hook() */
if (s5p_reset_hook)
s5p_reset_hook();
/* Perform reset using Watchdog reset
* if there is no s5p_reset_hook()
*/
arch_wdt_reset();
}
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