Commit f2cdb2e7 authored by Gary Bisson's avatar Gary Bisson Committed by Luis Henriques

ARM: clk-imx6q: fix video divider for rev T0 1.0

commit 81ef4479 upstream.

The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed
to 1. As the table index was wrong, a divider a of 4 could still be
requested which implied the clock not to be set properly. This is the
root cause of the HDMI not working at high resolution on rev T0 1.0 of
the SoC.
Signed-off-by: default avatarGary Bisson <bisson.gary@gmail.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarLuis Henriques <luis.henriques@canonical.com>
parent 50fc2a75
...@@ -163,7 +163,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -163,7 +163,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
post_div_table[1].div = 1; post_div_table[1].div = 1;
post_div_table[2].div = 1; post_div_table[2].div = 1;
video_div_table[1].div = 1; video_div_table[1].div = 1;
video_div_table[2].div = 1; video_div_table[3].div = 1;
} }
/* type name parent_name base div_mask */ /* type name parent_name base div_mask */
......
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