Commit f3d711aa authored by joe@perches.com's avatar joe@perches.com Committed by Paul Mackerras

[POWERPC] include/asm-ppc/: Spelling fixes

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent c90e1096
...@@ -123,7 +123,7 @@ typedef struct mem_ctlr { ...@@ -123,7 +123,7 @@ typedef struct mem_ctlr {
#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
#define OR_BI 0x00000100 /* Burst inhibit */ #define OR_BI 0x00000100 /* Burst inhibit */
#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ #define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
......
...@@ -681,7 +681,7 @@ typedef struct risc_timer_pram { ...@@ -681,7 +681,7 @@ typedef struct risc_timer_pram {
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
......
...@@ -283,7 +283,7 @@ ...@@ -283,7 +283,7 @@
#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ #define ESR_PPR 0x04000000 /* Program Exception - Privileged */
#define ESR_PTR 0x02000000 /* Program Exception - Trap */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */
#define ESR_FP 0x01000000 /* Floating Point Operation */ #define ESR_FP 0x01000000 /* Floating Point Operation */
#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
......
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