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Commit f4f1c8d9 authored by Neil Armstrong's avatar Neil Armstrong Committed by Kevin Hilman
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arm64: dts: meson-g12: add Everything-Else power domain controller 

Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent f9717178
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Showing with 78 additions and 48 deletions
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View file @ f4f1c8d9
......@@ -1406,6 +1406,53 @@ clkc: clock-controller {
clocks = <&xtal>;
clock-names = "xtal";
};
pwrc: power-controller {
compatible = "amlogic,meson-g12a-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&rti>;
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_BT656>,
<&reset RESET_RDMA>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC>,
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
reset-names = "viu", "venc", "vcbus", "bt656",
"rdma", "venci", "vencp", "vdac",
"vdi6", "vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
};
};
......@@ -1753,50 +1800,6 @@ clkc_AO: clock-controller {
clock-names = "xtal", "mpeg-clk";
};
pwrc_vpu: power-controller-vpu {
compatible = "amlogic,meson-g12a-pwrc-vpu";
#power-domain-cells = <0>;
amlogic,hhi-sysctrl = <&hhi>;
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_BT656>,
<&reset RESET_RDMA>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC>,
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
ao_pinctrl: pinctrl@14 {
compatible = "amlogic,meson-g12a-aobus-pinctrl";
#address-cells = <2>;
......@@ -2149,7 +2152,6 @@ vpu: vpu@ff900000 {
#address-cells = <1>;
#size-cells = <0>;
amlogic,canvas = <&canvas>;
power-domains = <&pwrc_vpu>;
/* CVBS VDAC output port */
cvbs_vdac_port: port@0 {
......
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View file @ f4f1c8d9
......@@ -4,6 +4,7 @@
*/
#include "meson-g12-common.dtsi"
#include <dt-bindings/power/meson-g12a-power.h>
/ {
compatible = "amlogic,g12a";
......@@ -110,6 +111,14 @@ opp-1800000000 {
};
};
&ethmac {
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};
&vpu {
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};
&sd_emmc_a {
amlogic,dram-access-quirk;
};
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
View file @ f4f1c8d9
......@@ -5,6 +5,7 @@
*/
#include "meson-g12-common.dtsi"
#include <dt-bindings/power/meson-g12a-power.h>
/ {
compatible = "amlogic,g12b";
......@@ -101,6 +102,14 @@ &clkc {
compatible = "amlogic,g12b-clkc";
};
&ethmac {
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};
&vpu {
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};
&sd_emmc_a {
amlogic,dram-access-quirk;
};
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View file @ f4f1c8d9
......@@ -5,6 +5,7 @@
*/
#include "meson-g12-common.dtsi"
#include <dt-bindings/power/meson-sm1-power.h>
/ {
compatible = "amlogic,sm1";
......@@ -59,10 +60,19 @@ &clk_msr {
compatible = "amlogic,meson-sm1-clk-measure";
};
&pwrc_vpu {
status = "disabled";
&ethmac {
power-domains = <&pwrc PWRC_SM1_ETH_ID>;
};
&pwrc {
compatible = "amlogic,meson-sm1-pwrc";
};
&vpu {
status = "disabled";
power-domains = <&pwrc PWRC_SM1_VPU_ID>;
};
&usb {
power-domains = <&pwrc PWRC_SM1_USB_ID>;
};
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