Commit f504f5f6 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville

ath9k_hw: fix a few inconsistencies in initval array names

Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 88c1f4f6
...@@ -1217,7 +1217,7 @@ static const u32 ar5416Addac_9160[][2] = { ...@@ -1217,7 +1217,7 @@ static const u32 ar5416Addac_9160[][2] = {
{0x000098cc, 0x00000000 }, {0x000098cc, 0x00000000 },
}; };
static const u32 ar5416Addac_91601_1[][2] = { static const u32 ar5416Addac_9160_1_1[][2] = {
{0x0000989c, 0x00000000 }, {0x0000989c, 0x00000000 },
{0x0000989c, 0x00000000 }, {0x0000989c, 0x00000000 },
{0x0000989c, 0x00000000 }, {0x0000989c, 0x00000000 },
......
...@@ -179,8 +179,8 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) ...@@ -179,8 +179,8 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
ARRAY_SIZE(ar5416Bank7_9160), 2); ARRAY_SIZE(ar5416Bank7_9160), 2);
if (AR_SREV_9160_11(ah)) { if (AR_SREV_9160_11(ah)) {
INIT_INI_ARRAY(&ah->iniAddac, INIT_INI_ARRAY(&ah->iniAddac,
ar5416Addac_91601_1, ar5416Addac_9160_1_1,
ARRAY_SIZE(ar5416Addac_91601_1), 2); ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
} else { } else {
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
ARRAY_SIZE(ar5416Addac_9160), 2); ARRAY_SIZE(ar5416Addac_9160), 2);
...@@ -239,12 +239,12 @@ void ar9002_hw_cck_chan14_spread(struct ath_hw *ah) ...@@ -239,12 +239,12 @@ void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
{ {
if (AR_SREV_9287_11_OR_LATER(ah)) { if (AR_SREV_9287_11_OR_LATER(ah)) {
INIT_INI_ARRAY(&ah->iniCckfirNormal, INIT_INI_ARRAY(&ah->iniCckfirNormal,
ar9287Common_normal_cck_fir_coeff_92871_1, ar9287Common_normal_cck_fir_coeff_9287_1_1,
ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
2); 2);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9287Common_japan_2484_cck_fir_coeff_92871_1, ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
2); 2);
} }
} }
......
...@@ -4142,13 +4142,13 @@ static const u32 ar9287Common_9287_1_1[][2] = { ...@@ -4142,13 +4142,13 @@ static const u32 ar9287Common_9287_1_1[][2] = {
* registers be programmed differently from the channel between 2412 and * registers be programmed differently from the channel between 2412 and
* 2472 MHz. * 2472 MHz.
*/ */
static const u32 ar9287Common_normal_cck_fir_coeff_92871_1[][2] = { static const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2] = {
{ 0x0000a1f4, 0x00fffeff }, { 0x0000a1f4, 0x00fffeff },
{ 0x0000a1f8, 0x00f5f9ff }, { 0x0000a1f8, 0x00f5f9ff },
{ 0x0000a1fc, 0xb79f6427 }, { 0x0000a1fc, 0xb79f6427 },
}; };
static const u32 ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = { static const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = {
{ 0x0000a1f4, 0x00000000 }, { 0x0000a1f4, 0x00000000 },
{ 0x0000a1f8, 0xefff0301 }, { 0x0000a1f8, 0xefff0301 },
{ 0x0000a1fc, 0xca9228ee }, { 0x0000a1fc, 0xca9228ee },
......
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