Commit f5aa19a4 authored by Lucas Stach's avatar Lucas Stach Committed by Ben Hutchings

PCI: imx6: Remove broken Gen2 workaround

commit a77c5422 upstream.

Remove the remnants of the workaround for erratum ERR005184 which was never
completely implemented.  The checks alone don't carry any value as we don't
act properly on the result.

A workaround should be added to the lane speed change in establish_link
later.
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
parent 79a85423
...@@ -427,7 +427,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp) ...@@ -427,7 +427,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
static int imx6_pcie_link_up(struct pcie_port *pp) static int imx6_pcie_link_up(struct pcie_port *pp)
{ {
u32 rc, debug_r0, rx_valid; u32 rc;
int count = 5; int count = 5;
/* /*
...@@ -461,21 +461,6 @@ static int imx6_pcie_link_up(struct pcie_port *pp) ...@@ -461,21 +461,6 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
*/ */
usleep_range(1000, 2000); usleep_range(1000, 2000);
} }
/*
* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
* If (MAC/LTSSM.state == Recovery.RcvrLock)
* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
* to gen2 is stuck
*/
pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
if (rx_valid & 0x01)
return 0;
if ((debug_r0 & 0x3f) != 0x0d)
return 0;
return 0; return 0;
} }
......
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