Commit f5e5afdb authored by Clark Wang's avatar Clark Wang Committed by Mark Brown

spi: lpspi: Add i.MX8 boards support for lpspi

Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards.
Signed-off-by: default avatarClark Wang <xiaoning.wang@nxp.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 2e541b64
......@@ -84,7 +84,8 @@ struct lpspi_config {
struct fsl_lpspi_data {
struct device *dev;
void __iomem *base;
struct clk *clk;
struct clk *clk_ipg;
struct clk *clk_per;
bool is_slave;
void *rx_buf;
......@@ -151,8 +152,19 @@ static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
{
struct fsl_lpspi_data *fsl_lpspi =
spi_controller_get_devdata(controller);
int ret;
ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
if (ret)
return ret;
ret = clk_prepare_enable(fsl_lpspi->clk_per);
if (ret) {
clk_disable_unprepare(fsl_lpspi->clk_ipg);
return ret;
}
return clk_prepare_enable(fsl_lpspi->clk);
return 0;
}
static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
......@@ -160,7 +172,8 @@ static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
struct fsl_lpspi_data *fsl_lpspi =
spi_controller_get_devdata(controller);
clk_disable_unprepare(fsl_lpspi->clk);
clk_disable_unprepare(fsl_lpspi->clk_ipg);
clk_disable_unprepare(fsl_lpspi->clk_per);
return 0;
}
......@@ -241,7 +254,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
unsigned int perclk_rate, scldiv;
u8 prescale;
perclk_rate = clk_get_rate(fsl_lpspi->clk);
perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
for (prescale = 0; prescale < 8; prescale++) {
scldiv = perclk_rate /
(clkdivs[prescale] * config.speed_hz) - 2;
......@@ -526,15 +539,30 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
goto out_controller_put;
}
fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(fsl_lpspi->clk)) {
ret = PTR_ERR(fsl_lpspi->clk);
fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(fsl_lpspi->clk_per)) {
ret = PTR_ERR(fsl_lpspi->clk_per);
goto out_controller_put;
}
fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(fsl_lpspi->clk_ipg)) {
ret = PTR_ERR(fsl_lpspi->clk_ipg);
goto out_controller_put;
}
ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
if (ret) {
dev_err(&pdev->dev,
"can't enable lpspi ipg clock, ret=%d\n", ret);
goto out_controller_put;
}
ret = clk_prepare_enable(fsl_lpspi->clk);
ret = clk_prepare_enable(fsl_lpspi->clk_per);
if (ret) {
dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
dev_err(&pdev->dev,
"can't enable lpspi per clock, ret=%d\n", ret);
clk_disable_unprepare(fsl_lpspi->clk_ipg);
goto out_controller_put;
}
......@@ -542,7 +570,8 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
clk_disable_unprepare(fsl_lpspi->clk);
clk_disable_unprepare(fsl_lpspi->clk_per);
clk_disable_unprepare(fsl_lpspi->clk_ipg);
ret = devm_spi_register_controller(&pdev->dev, controller);
if (ret < 0) {
......@@ -564,7 +593,8 @@ static int fsl_lpspi_remove(struct platform_device *pdev)
struct fsl_lpspi_data *fsl_lpspi =
spi_controller_get_devdata(controller);
clk_disable_unprepare(fsl_lpspi->clk);
clk_disable_unprepare(fsl_lpspi->clk_per);
clk_disable_unprepare(fsl_lpspi->clk_ipg);
return 0;
}
......
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