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Commit f6eb8139 authored by David S. Miller's avatar David S. Miller
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Merge nuts.davemloft.net:/disk1/BK/network-2.6 

into nuts.davemloft.net:/disk1/BK/net-2.6
parents cd0e8af5 cab892f9
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Showing with 2825 additions and 4703 deletions
arch/alpha/kernel/core_apecs.c
View file @ f6eb8139
......@@ -10,20 +10,18 @@
* Code common to all APECS core logic chips.
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_apecs.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/smp.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_apecs.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_cia.c
View file @ f6eb8139
......@@ -11,23 +11,19 @@
* Code common to all CIA core logic chips.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/hwrpb.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_cia.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/ptrace.h>
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_irongate.c
View file @ f6eb8139
......@@ -9,27 +9,23 @@
* Code common to all IRONGATE core logic chips.
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_irongate.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/initrd.h>
#include <linux/bootmem.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/pci.h>
#include <asm/hwrpb.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_irongate.h>
#undef __EXTERN_INLINE
#include <linux/bootmem.h>
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_lca.c
View file @ f6eb8139
......@@ -8,21 +8,19 @@
* Code common to all LCA core logic chips.
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_lca.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/tty.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/smp.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_lca.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_marvel.c
View file @ f6eb8139
......@@ -4,14 +4,11 @@
* Code common to all Marvel based systems.
*/
#include <linux/config.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_marvel.h>
#undef __EXTERN_INLINE
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
......@@ -20,18 +17,15 @@
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/bootmem.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/smp.h>
#include <asm/hwrpb.h>
#include <asm/gct.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#include <asm/rtc.h>
#include <linux/bootmem.h>
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_mcpcia.c
View file @ f6eb8139
......@@ -6,7 +6,11 @@
* Code common to all MCbus-PCI Adaptor core logic chipsets
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_mcpcia.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
......@@ -14,13 +18,6 @@
#include <linux/delay.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/hwrpb.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_mcpcia.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_polaris.c
View file @ f6eb8139
......@@ -4,20 +4,18 @@
* POLARIS chip-specific code
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_polaris.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_polaris.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_t2.c
View file @ f6eb8139
......@@ -9,21 +9,19 @@
* Code common to all T2 core logic chips.
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE
#include <asm/io.h>
#include <asm/core_t2.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/delay.h>
#define __EXTERN_INLINE
#include <asm/io.h>
#include <asm/core_t2.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_titan.c
View file @ f6eb8139
......@@ -4,29 +4,24 @@
* Code common to all TITAN core logic chips.
*/
#include <linux/config.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_titan.h>
#undef __EXTERN_INLINE
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/bootmem.h>
#include <asm/hwrpb.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/smp.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_titan.h>
#undef __EXTERN_INLINE
#include <linux/bootmem.h>
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_tsunami.c
View file @ f6eb8139
......@@ -6,23 +6,20 @@
* Code common to all TSUNAMI core logic chips.
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_tsunami.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/smp.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_tsunami.h>
#undef __EXTERN_INLINE
#include <linux/bootmem.h>
#include "proto.h"
#include "pci_impl.h"
......
arch/alpha/kernel/core_wildfire.c
View file @ f6eb8139
......@@ -6,21 +6,19 @@
* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
*/
#include <linux/kernel.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_wildfire.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/smp.h>
#define __EXTERN_INLINE inline
#include <asm/io.h>
#include <asm/core_wildfire.h>
#undef __EXTERN_INLINE
#include "proto.h"
#include "pci_impl.h"
......
arch/arm/kernel/time.c
View file @ f6eb8139
......@@ -72,8 +72,10 @@ unsigned long (*gettimeoffset)(void) = dummy_gettimeoffset;
/*
* Scheduler clock - returns current time in nanosec units.
* This is the default implementation. Sub-architecture
* implementations can override this.
*/
unsigned long long sched_clock(void)
unsigned long long __attribute__((weak)) sched_clock(void)
{
return (unsigned long long)jiffies * (1000000000 / HZ);
}
......
arch/i386/Kconfig
View file @ f6eb8139
......@@ -701,7 +701,7 @@ config X86_PAE
# Common NUMA Features
config NUMA
bool "Numa Memory Allocation Support"
depends on SMP && HIGHMEM64G && (X86_PC || X86_NUMAQ || X86_GENERICARCH || (X86_SUMMIT && ACPI && !ACPI_HT_ONLY))
depends on SMP && HIGHMEM64G && (X86_PC || X86_NUMAQ || X86_GENERICARCH || (X86_SUMMIT && ACPI))
default n if X86_PC
default y if (X86_NUMAQ || X86_SUMMIT)
......@@ -709,8 +709,8 @@ config NUMA
comment "NUMA (NUMA-Q) requires SMP, 64GB highmem support"
depends on X86_NUMAQ && (!HIGHMEM64G || !SMP)
comment "NUMA (Summit) requires SMP, 64GB highmem support, full ACPI"
depends on X86_SUMMIT && (!HIGHMEM64G || !ACPI || ACPI_HT_ONLY)
comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
depends on X86_SUMMIT && (!HIGHMEM64G || !ACPI)
config DISCONTIGMEM
bool
......
arch/i386/kernel/acpi/boot.c
View file @ f6eb8139
......@@ -141,6 +141,10 @@ acpi_parse_lapic (
acpi_table_print_madt_entry(header);
/* no utility in registering a disabled processor */
if (processor->flags.enabled == 0)
return 0;
mp_register_lapic (
processor->id, /* APIC ID */
processor->flags.enabled); /* Enabled? */
......
arch/i386/kernel/mpparse.c
View file @ f6eb8139
......@@ -634,7 +634,7 @@ void __init get_smp_config (void)
/*
* ACPI may be used to obtain the entire SMP configuration or just to
* enumerate/configure processors (CONFIG_ACPI_HT). Note that
* enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
* ACPI supports both logical (e.g. Hyper-Threading) and physical
* processors, where MPS only supports physical.
*/
......@@ -940,7 +940,7 @@ void __init mp_override_legacy_irq (
* erroneously sets the trigger to level, resulting in a HUGE
* increase of timer interrupts!
*/
if ((bus_irq == 0) && (global_irq == 2) && (trigger == 3))
if ((bus_irq == 0) && (trigger == 3))
trigger = 1;
intsrc.mpc_type = MP_INTSRC;
......@@ -961,7 +961,7 @@ void __init mp_override_legacy_irq (
* Otherwise create a new entry (e.g. global_irq == 2).
*/
for (i = 0; i < mp_irq_entries; i++) {
if ((mp_irqs[i].mpc_dstapic == intsrc.mpc_dstapic)
if ((mp_irqs[i].mpc_srcbus == intsrc.mpc_srcbus)
&& (mp_irqs[i].mpc_srcbusirq == intsrc.mpc_srcbusirq)) {
mp_irqs[i] = intsrc;
found = 1;
......@@ -1008,9 +1008,10 @@ void __init mp_config_acpi_legacy_irqs (void)
*/
for (i = 0; i < 16; i++) {
if (i == 2) continue; /* Don't connect IRQ2 */
if (i == 2)
continue; /* Don't connect IRQ2 */
intsrc.mpc_irqtype = i ? mp_INT : mp_ExtINT; /* 8259A to #0 */
intsrc.mpc_irqtype = mp_INT;
intsrc.mpc_srcbusirq = i; /* Identity mapped */
intsrc.mpc_dstirq = i;
......
arch/ppc/Kconfig
View file @ f6eb8139
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765
depends on SANDPOINT || MCPN765 || SPRUCE
default y
config FORCE
......
arch/ppc/boot/common/bootinfo.c 0 → 100644
View file @ f6eb8139
/*
* arch/ppc/common/bootinfo.c
*
* General bootinfo record utilities
* Author: Randy Vinson <rvinson@mvista.com>
*
* 2002 (c) MontaVista Software, Inc. This file is licensed under the terms
* of the GNU General Public License version 2. This program is licensed
* "as is" without any warranty of any kind, whether express or implied.
*/
#include <linux/types.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
#include "nonstdio.h"
static struct bi_record * birec = NULL;
static struct bi_record *
__bootinfo_build(struct bi_record *rec, unsigned long tag, unsigned long size,
void *data)
{
/* set the tag */
rec->tag = tag;
/* if the caller has any data, copy it */
if (size)
memcpy(rec->data, (char *)data, size);
/* set the record size */
rec->size = sizeof(struct bi_record) + size;
/* advance to the next available space */
rec = (struct bi_record *)((unsigned long)rec + rec->size);
return rec;
}
void
bootinfo_init(struct bi_record *rec)
{
/* save start of birec area */
birec = rec;
/* create an empty list */
rec = __bootinfo_build(rec, BI_FIRST, 0, NULL);
(void) __bootinfo_build(rec, BI_LAST, 0, NULL);
}
void
bootinfo_append(unsigned long tag, unsigned long size, void * data)
{
struct bi_record *rec = birec;
/* paranoia */
if ((rec == NULL) || (rec->tag != BI_FIRST))
return;
/* find the last entry in the list */
while (rec->tag != BI_LAST)
rec = (struct bi_record *)((ulong)rec + rec->size);
/* overlay BI_LAST record with new one and tag on a new BI_LAST */
rec = __bootinfo_build(rec, tag, size, data);
(void) __bootinfo_build(rec, BI_LAST, 0, NULL);
}
arch/ppc/boot/simple/Makefile
View file @ f6eb8139
......@@ -30,7 +30,7 @@ tftpboot := /tftpboot
# Normally, we use the 'misc.c' file for decompress_kernel and
# whatnot. Sometimes we need to override this however.
misc-y := misc.o
misc-y := misc.o ../common/bootinfo.o
# Normally, we have our images end in .elf, but something we want to
# change this.
......@@ -103,7 +103,7 @@ zimageinitrd-$(pcore) := zImage.initrd-STRIPELF
zimageinitrd-$(CONFIG_SPRUCE) := zImage.initrd-TREE
end-$(CONFIG_SPRUCE) := spruce
entrypoint-$(CONFIG_SPRUCE) := 0x00800000
misc-$(CONFIG_SPRUCE) := misc-spruce.o
misc-$(CONFIG_SPRUCE) += misc-spruce.o
# SMP images should have a '.smp' suffix.
end-$(CONFIG_SMP) += .smp
......
arch/ppc/boot/simple/misc-spruce.c
View file @ f6eb8139
......@@ -15,55 +15,19 @@
*/
#include <linux/types.h>
#include <linux/elf.h>
#include <linux/config.h>
#include <linux/pci.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/bootinfo.h>
#include "zlib.h"
extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
unsigned long cksum);
/* Define some important locations of the Spruce. */
#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
#define SPRUCE_PCI_CONFIG_DATA 0xfec00004
#define SPRUCE_ISA_IO_BASE 0xf8000000
unsigned long com_port;
char *avail_ram;
char *end_avail;
/* The linker tells us where the image is. */
extern char __image_begin, __image_end;
extern char __ramdisk_begin, __ramdisk_end;
extern char _end[];
#ifdef CONFIG_CMDLINE
#define CMDLINE CONFIG_CMDLINE
#else
#define CMDLINE ""
#endif
char cmd_preset[] = CMDLINE;
char cmd_buf[256];
char *cmd_line = cmd_buf;
unsigned long initrd_size = 0;
char *zimage_start;
int zimage_size;
extern void udelay(long);
extern void puts(const char *);
extern void putc(const char c);
extern void puthex(unsigned long val);
extern int getc(void);
extern int tstc(void);
extern void gunzip(void *, int, unsigned char *, int *);
extern unsigned long serial_init(int chan, void *ignored);
/* PCI configuration space access routines. */
unsigned int *pci_config_address = (unsigned int *)SPRUCE_PCI_CONFIG_ADDR;
unsigned char *pci_config_data = (unsigned char *)SPRUCE_PCI_CONFIG_DATA;
......@@ -146,45 +110,16 @@ unsigned long isa_io_base = SPRUCE_ISA_IO_BASE;
#define MEM_B2EA 0x60
unsigned long
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
get_mem_size(void)
{
int timer = 0;
char *cp, ch;
int loop;
int csr0;
int csr_id;
int *mem_addr = (int *)0xff500008;
int *mem_data = (int *)0xff50000c;
int mem_size = 0;
unsigned long mem_size = 0;
unsigned long mem_mben;
unsigned long mem_type;
unsigned long mem_start;
unsigned long mem_end;
int *pif_addr = (int *)0xff500000;
int *pif_data = (int *)0xff500004;
int pci_devfn;
int found_multi = 0;
unsigned short vendor;
unsigned short device;
unsigned short command;
unsigned char header_type;
unsigned int bar0;
#ifdef CONFIG_SERIAL_8250_CONSOLE
/* Initialize the serial console port */
com_port = serial_init(0, NULL);
#endif
/*
* Gah, these firmware guys need to learn that hardware
* byte swapping is evil! Disable all hardware byte
* swapping so it doesn't hurt anyone.
*/
*pif_addr = PLBMIFOPT;
asm("sync");
*pif_data = 0x00000000;
asm("sync");
volatile int *mem_addr = (int *)0xff500008;
volatile int *mem_data = (int *)0xff50000c;
/* Get the size of memory from the memory controller. */
*mem_addr = MEM_MBEN;
......@@ -235,6 +170,33 @@ load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
mem_size += mem_end - mem_start + 0x100000;
}
return mem_size;
}
unsigned long
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
{
int csr0;
int csr_id;
int pci_devfn;
int found_multi = 0;
unsigned short vendor;
unsigned short device;
unsigned short command;
unsigned char header_type;
unsigned int bar0;
volatile int *pif_addr = (int *)0xff500000;
volatile int *pif_data = (int *)0xff500004;
/*
* Gah, these firmware guys need to learn that hardware
* byte swapping is evil! Disable all hardware byte
* swapping so it doesn't hurt anyone.
*/
*pif_addr = PLBMIFOPT;
asm("sync");
*pif_data = 0x00000000;
asm("sync");
/* Search out and turn off the PcNet ethernet boot device. */
for (pci_devfn = 1; pci_devfn < 0xff; pci_devfn++) {
......@@ -310,134 +272,5 @@ load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
}
}
/* assume the chunk below 8M is free */
end_avail = (char *)0x00800000;
/*
* We link ourself to 0x00800000. When we run, we relocate
* ourselves there. So we just need __image_begin for the
* start. -- Tom
*/
zimage_start = (char *)(unsigned long)(&__image_begin);
zimage_size = (unsigned long)(&__image_end) -
(unsigned long)(&__image_begin);
initrd_size = (unsigned long)(&__ramdisk_end) -
(unsigned long)(&__ramdisk_begin);
/*
* The zImage and initrd will be between start and _end, so they've
* already been moved once. We're good to go now. -- Tom
*/
avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
puts("zimage at: "); puthex((unsigned long)zimage_start);
puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
puts("\n");
if ( initrd_size ) {
puts("initrd at: ");
puthex((unsigned long)(&__ramdisk_begin));
puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
}
avail_ram = (char *)0x00400000;
end_avail = (char *)0x00800000;
puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
puthex((unsigned long)end_avail); puts("\n");
/* Display standard Linux/PPC boot prompt for kernel args */
puts("\nLinux/PPC load: ");
cp = cmd_line;
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
while ( *cp ) putc(*cp++);
while (timer++ < 5*1000) {
if (tstc()) {
while ((ch = getc()) != '\n' && ch != '\r') {
if (ch == '\b') {
if (cp != cmd_line) {
cp--;
puts("\b \b");
}
} else {
*cp++ = ch;
putc(ch);
}
}
break; /* Exit 'timer' loop */
}
udelay(1000); /* 1 msec */
}
*cp = 0;
puts("\n");
puts("Uncompressing Linux...");
gunzip(0, 0x400000, zimage_start, &zimage_size);
puts("done.\n");
{
struct bi_record *rec;
unsigned long initrd_loc;
unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) +
(1 << 20) - 1, (1 << 20));
rec = (struct bi_record *)rec_loc;
/* We need to make sure that the initrd and bi_recs do not
* overlap. */
if ( initrd_size ) {
initrd_loc = (unsigned long)(&__ramdisk_begin);
/* If the bi_recs are in the middle of the current
* initrd, move the initrd to the next MB
* boundary. */
if ((rec_loc > initrd_loc) &&
((initrd_loc + initrd_size)
> rec_loc)) {
initrd_loc = _ALIGN((unsigned long)(zimage_size)
+ (2 << 20) - 1, (2 << 20));
memmove((void *)initrd_loc, &__ramdisk_begin,
initrd_size);
puts("initrd moved: "); puthex(initrd_loc);
puts(" "); puthex(initrd_loc + initrd_size);
puts("\n");
}
}
rec->tag = BI_FIRST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_BOOTLOADER_ID;
memcpy( (void *)rec->data, "spruceboot", 11);
rec->size = sizeof(struct bi_record) + 10 + 1;
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_MEMSIZE;
rec->data[0] = mem_size;
rec->size = sizeof(struct bi_record) + sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_CMD_LINE;
memcpy( (char *)rec->data, cmd_line, strlen(cmd_line)+1);
rec->size = sizeof(struct bi_record) + strlen(cmd_line) + 1;
rec = (struct bi_record *)((ulong)rec + rec->size);
if ( initrd_size ) {
rec->tag = BI_INITRD;
rec->data[0] = initrd_loc;
rec->data[1] = initrd_size;
rec->size = sizeof(struct bi_record) + 2 *
sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec +
rec->size);
}
rec->tag = BI_LAST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
}
puts("Now booting the kernel\n");
return 0;
return decompress_kernel(load_addr, num_words, cksum);
}
arch/ppc/boot/simple/misc.c
View file @ f6eb8139
/*
* arch/ppc/common/misc-simple.c
* arch/ppc/simple/misc.c
*
* Misc. bootloader code for many machines. This assumes you have are using
* a 6xx/7xx/74xx CPU in your machine. This assumes the chunk of memory
......@@ -46,6 +46,15 @@
#define HAS_KEYB 0
#endif
/* Will / Can the user give input?
* Val Henson has requested that Gemini doesn't wait for the
* user to edit the cmdline or not.
*/
#if (defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
#endif
char *avail_ram;
char *end_avail;
char *zimage_start;
......@@ -66,19 +75,28 @@ extern char _end[];
extern unsigned long start;
extern int CRT_tstc(void);
extern unsigned long get_mem_size(void);
extern unsigned long serial_init(int chan, void *ignored);
extern void serial_close(unsigned long com_port);
extern void gunzip(void *, int, unsigned char *, int *);
extern void serial_fixups(void);
/* Allow get_mem_size to be hooked into. This is the default. */
unsigned long __attribute__ ((weak))
get_mem_size(void)
{
return 0;
}
struct bi_record *
decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
{
#ifdef INTERACTIVE_CONSOLE
int timer = 0;
char *cp, ch;
char ch;
#endif
char *cp;
struct bi_record *rec;
unsigned long TotalMemory = 0, rec_loc, initrd_loc;
unsigned long initrd_loc, TotalMemory = 0;
serial_fixups();
com_port = serial_init(0, NULL);
......@@ -93,13 +111,11 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
__asm__ __volatile__("eieio");
#endif
#if defined(CONFIG_LOPEC) || defined(CONFIG_PAL4)
/*
* Call get_mem_size(), which is memory controller dependent,
* and we must have the correct file linked in here.
*/
TotalMemory = get_mem_size();
#endif
/* assume the chunk below 8M is free */
end_avail = (char *)0x00800000;
......@@ -170,9 +186,11 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
while ( *cp ) putc(*cp++);
#ifndef CONFIG_GEMINI
/* Val Henson has requested that Gemini doesn't wait for the
* user to edit the cmdline or not. */
#ifdef INTERACTIVE_CONSOLE
/*
* If they have a console, allow them to edit the command line.
* Otherwise, don't bother wasting the five seconds.
*/
while (timer++ < 5*1000) {
if (tstc()) {
while ((ch = getc()) != '\n' && ch != '\r') {
......@@ -205,16 +223,13 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
gunzip(0, 0x400000, zimage_start, &zimage_size);
puts("done.\n");
/*
* Create bi_recs for cmd_line and initrds
*/
rec_loc = _ALIGN((unsigned long)(zimage_size) +
(1 << 20) - 1, (1 << 20));
rec = (struct bi_record *)rec_loc;
/* get the bi_rec address */
rec = bootinfo_addr(zimage_size);
/* We need to make sure that the initrd and bi_recs do not
* overlap. */
if ( initrd_size ) {
unsigned long rec_loc = (unsigned long) rec;
initrd_loc = (unsigned long)(&__ramdisk_begin);
/* If the bi_recs are in the middle of the current
* initrd, move the initrd to the next MB
......@@ -231,39 +246,25 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
}
}
rec->tag = BI_FIRST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
bootinfo_init(rec);
if ( TotalMemory )
bootinfo_append(BI_MEMSIZE, sizeof(int), (void*)&TotalMemory);
if ( TotalMemory ) {
rec->tag = BI_MEMSIZE;
rec->data[0] = TotalMemory;
rec->size = sizeof(struct bi_record) + sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
}
bootinfo_append(BI_CMD_LINE, strlen(cmd_line)+1, (void*)cmd_line);
rec->tag = BI_CMD_LINE;
memcpy( (char *)rec->data, cmd_line, strlen(cmd_line)+1);
rec->size = sizeof(struct bi_record) + strlen(cmd_line) + 1;
rec = (struct bi_record *)((unsigned long)rec + rec->size);
/* add a bi_rec for the initrd if it exists */
if (initrd_size) {
unsigned long initrd[2];
if ( initrd_size ) {
rec->tag = BI_INITRD;
rec->data[0] = initrd_loc;
rec->data[1] = initrd_size;
rec->size = sizeof(struct bi_record) + 2 *
sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec +
rec->size);
}
initrd[0] = initrd_loc;
initrd[1] = initrd_size;
rec->tag = BI_LAST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
bootinfo_append(BI_INITRD, sizeof(initrd), &initrd);
}
puts("Now booting the kernel\n");
serial_close(com_port);
return (struct bi_record *)rec_loc;
return rec;
}
/* Allow decompress_kernel to be hooked into. This is the default. */
......
arch/ppc/configs/spruce_defconfig
View file @ f6eb8139
......@@ -4,11 +4,17 @@
CONFIG_MMU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
......@@ -18,9 +24,15 @@ CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
#
# Loadable module support
......@@ -33,24 +45,25 @@ CONFIG_OBSOLETE_MODPARM=y
CONFIG_KMOD=y
#
# Platform support
# Processor
#
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_STD_MMU=y
#
# IBM 4xx options
# Platform options
#
# CONFIG_8260 is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_STD_MMU=y
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
# CONFIG_WILLOW_2 is not set
# CONFIG_WILLOW is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_EV64260 is not set
......@@ -66,35 +79,31 @@ CONFIG_SPRUCE=y
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_SPRUCE_BAUD_33M is not set
# CONFIG_EST8260 is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX6 is not set
# CONFIG_TQM8260 is not set
CONFIG_PPC_GEN550=y
CONFIG_SPRUCE_BAUD_33M=y
# CONFIG_SMP is not set
# CONFIG_PREEMPT is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_HIGHMEM is not set
CONFIG_KERNEL_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# General setup
# Bus options
#
# CONFIG_HIGHMEM is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_PCI_LEGACY_PROC=y
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
# CONFIG_PPC601_SYNC_FIX is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# Advanced setup
#
......@@ -109,15 +118,27 @@ CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Device Drivers
#
#
# Generic Driver Options
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
......@@ -131,21 +152,22 @@ CONFIG_BOOT_LOAD=0x00800000
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_LBD is not set
#
# Multi-device support (RAID and LVM)
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_MD is not set
# CONFIG_IDE is not set
#
# ATA/IDE/MFM/RLL support
# SCSI device support
#
# CONFIG_IDE is not set
# CONFIG_SCSI is not set
#
# SCSI support
# Multi-device support (RAID and LVM)
#
# CONFIG_SCSI is not set
# CONFIG_MD is not set
#
# Fusion MPT device support
......@@ -161,6 +183,10 @@ CONFIG_BOOT_LOAD=0x00800000
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
#
# Networking support
#
......@@ -172,7 +198,6 @@ CONFIG_NET=y
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK_DEV is not set
# CONFIG_NETFILTER is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
......@@ -191,7 +216,9 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_NETFILTER is not set
#
# SCTP Configuration (EXPERIMENTAL)
......@@ -200,9 +227,9 @@ CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
......@@ -230,13 +257,13 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_CRC32=y
# CONFIG_OAKNET is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
......@@ -252,6 +279,7 @@ CONFIG_PCNET32=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
# CONFIG_E100 is not set
......@@ -276,6 +304,7 @@ CONFIG_PCNET32=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
......@@ -294,8 +323,9 @@ CONFIG_PCNET32=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -315,19 +345,19 @@ CONFIG_PCNET32=y
# CONFIG_IRDA is not set
#
# ISDN subsystem
# Bluetooth support
#
# CONFIG_ISDN_BOOL is not set
# CONFIG_BT is not set
#
# Graphics support
# ISDN subsystem
#
# CONFIG_FB is not set
# CONFIG_ISDN_BOOL is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
......@@ -347,18 +377,16 @@ CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
CONFIG_SERIO_PCIPS2=y
#
# Input Device Drivers
#
#
# Macintosh device drivers
#
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
......@@ -366,6 +394,7 @@ CONFIG_SERIO_SERPORT=y
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......@@ -376,20 +405,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
......@@ -419,7 +434,11 @@ CONFIG_GEN_RTC=y
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Multimedia devices
......@@ -431,6 +450,26 @@ CONFIG_GEN_RTC=y
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# File systems
#
......@@ -470,10 +509,12 @@ CONFIG_ISO9660_FS=y
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
CONFIG_TMPFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
......@@ -498,6 +539,7 @@ CONFIG_RAMFS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
......@@ -518,31 +560,19 @@ CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
# Native Language Support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# CONFIG_NLS is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
#
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_KALLSYMS is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
# Security options
......
arch/ppc/kernel/entry.S
View file @ f6eb8139
......@@ -689,8 +689,8 @@ ret_from_crit_exc:
mtspr SPRN_ESR,r10
lwz r11,_NIP(r1)
lwz r12,_MSR(r1)
mtspr SRR2,r11
mtspr SRR3,r12
mtspr CSRR0,r11
mtspr CSRR1,r12
lwz r9,GPR9(r1)
lwz r12,GPR12(r1)
lwz r10,crit_sprg0@l(0)
......
arch/ppc/kernel/head_44x.S
View file @ f6eb8139
This diff is collapsed.
arch/ppc/kernel/misc.S
View file @ f6eb8139
......@@ -406,17 +406,18 @@ _GLOBAL(_tlbia)
tlbia
isync /* Flush shadow TLB */
#elif defined(CONFIG_44x)
lis r3,0
li r3,0
sync
1:
tlbwe r3,r3,PPC44x_TLB_PAGEID
addi r3,r3,1
/* Load high watermark */
lis r4,tlb_44x_hwater@h
ori r4,r4,tlb_44x_hwater@l
lwz r5,0(r4)
lis r4,tlb_44x_hwater@ha
lwz r5,tlb_44x_hwater@l(r4)
1: tlbwe r3,r3,PPC44x_TLB_PAGEID
addi r3,r3,1
cmpw 0,r3,r5
ble 1b
isync
#else /* !(CONFIG_40x || CONFIG_44x) */
#if defined(CONFIG_SMP)
......@@ -470,17 +471,10 @@ _GLOBAL(_tlbie)
isync
10:
#elif defined(CONFIG_44x)
mfspr r4,SPRN_MMUCR /* Get MMUCR */
lis r5,PPC44x_MMUCR_STS@h
ori r5,r5,PPC44x_MMUCR_TID@l /* Create mask */
andc r4,r4,r5 /* Clear out TID/STS bits */
mfspr r4,SPRN_MMUCR
mfspr r5,SPRN_PID /* Get PID */
or r4,r4,r5 /* Set TID bits */
mfmsr r6 /* Get MSR */
andi. r6,r6,MSR_IS@l /* TS=1? */
beq 11f /* If not, leave STS=0 */
oris r4,r4,PPC44x_MMUCR_STS@h /* Set STS=1 */
11: mtspr SPRN_MMUCR, r4 /* Put MMUCR */
rlwimi r4,r5,0,24,31 /* Set TID */
mtspr SPRN_MMUCR,r4
tlbsx. r3, 0, r3
bne 10f
......
arch/ppc/mm/44x_mmu.c
View file @ f6eb8139
......@@ -64,7 +64,7 @@ extern struct mem_pieces phys_avail;
* Just needed it declared someplace.
*/
unsigned int tlb_44x_index = 0;
unsigned int tlb_44x_hwater = 61;
unsigned int tlb_44x_hwater = 62;
/*
* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
......@@ -85,7 +85,7 @@ ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
tlbwe %0,%3,%8"
:
: "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
"i" (PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M)),
"i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
"i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
"i" (PPC44x_TLB_PAGEID),
"i" (PPC44x_TLB_XLAT),
......
arch/ppc/platforms/4xx/Kconfig
View file @ f6eb8139
......@@ -13,48 +13,43 @@ choice
config ASH
bool "Ash"
config BEECH
bool "Beech"
config CEDAR
bool "Cedar"
help
This option enables support for the IBM NP405H evaluation board.
config CPCI405
bool "CPCI405"
help
This option enables support for the CPCI405 board.
config EP405
bool "EP405/EP405PC"
help
This option enables support for the EP405/EP405PC boards.
config OAK
bool "Oak"
help
Select Oak if you have an IBM 403GCX "Oak" Evaluation Board.
Select Walnut if you have an IBM 405GP "Walnut" Evaluation Board.
More information on these boards is available at:
<http://www.chips.ibm.com/products/powerpc/tools/evk_pn.html#GCX>.
config REDWOOD_4
bool "Redwood-4"
This option enables support for the IBM 403GCX evaluation board.
config REDWOOD_5
bool "Redwood-5"
help
This option enables support for the IBM STB04 evaluation board.
config REDWOOD_6
bool "Redwood-6"
help
This option enables support for the IBM STBx25xx evaluation board.
config SYCAMORE
bool "Sycamore"
config TIVO
bool "Tivo"
help
This option enables support for the IBM PPC405GPr evaluation board.
config WALNUT
bool "Walnut"
help
Select Walnut if you have an IBM 405GP "Walnut" Evaluation Board.
This option enables support for the IBM PPC405GP evaluation board.
endchoice
......@@ -120,12 +115,6 @@ config IBM405_ERR51
depends on 40x && !405GPR
default y
config PIN_TLB
bool
depends on 44x
default y
config BOOKE
bool
depends on 44x
......@@ -133,7 +122,7 @@ config BOOKE
config IBM_OCP
bool
depends on ASH || BEECH || CEDAR || CPCI405 || EBONY || EP405 || OCOTEA || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
depends on ASH || CPCI405 || EBONY || EP405 || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
default y
config IBM_EMAC4
......@@ -141,19 +130,14 @@ config IBM_EMAC4
depends on 440GX
default y
config NP405L
bool
depends on CEDAR
default y
config BIOS_FIXUP
bool
depends on CEDAR || EP405 || SYCAMORE || WALNUT
depends on EP405 || SYCAMORE || WALNUT
default y
config 403GCX
bool
depends OAK || TIVO
depends OAK
default y
config 405GP
......@@ -165,13 +149,9 @@ config 405GPR
bool
depends on SYCAMORE
config 405LP
bool
depends on CEDAR
config STB03xxx
bool
depends on REDWOOD_5 || REDWOOD_4 || REDWOOD_6
depends on REDWOOD_5 || REDWOOD_6
default y
config EMBEDDEDBOOT
......@@ -181,13 +161,9 @@ config EMBEDDEDBOOT
config IBM_OPENBIOS
bool
depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
depends on ASH || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
default y
config 405_DMA
bool "Blue Logic DMA"
depends on 40x
config PM
bool "Power Management support (EXPERIMENTAL)"
depends on 4xx && EXPERIMENTAL
......
arch/ppc/platforms/4xx/Makefile
View file @ f6eb8139
......@@ -2,27 +2,20 @@
# Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
obj-$(CONFIG_BEECH) += beech.o
obj-$(CONFIG_CEDAR) += cedar.o
obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_OAK) += oak.o
obj-$(CONFIG_OCOTEA) += ocotea.o
obj-$(CONFIG_REDWOOD_4) += redwood.o
obj-$(CONFIG_REDWOOD_5) += redwood5.o
obj-$(CONFIG_REDWOOD_6) += redwood6.o
obj-$(CONFIG_SYCAMORE) += sycamore.o
obj-$(CONFIG_WALNUT) += walnut.o
obj-$(CONFIG_NP405L) += ibmnp405l.o
obj-$(CONFIG_405GP) += ibm405gp.o
obj-$(CONFIG_REDWOOD_4) += ibmstb3.o
obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
obj-$(CONFIG_NP405H) += ibmnp405h.o
obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
obj-$(CONFIG_NP4GS3) += ibmnp4gs.o
obj-$(CONFIG_405LP) += ibm405lp.o
obj-$(CONFIG_EBONY) += ibm440gp.o
obj-$(CONFIG_OCOTEA) += ibm440gx.o
obj-$(CONFIG_405GPR) += ibm405gpr.o
arch/ppc/platforms/4xx/beech.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/beech.c Platform setup for the IBM Beech board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/param.h>
#include <linux/rtc.h>
#include <linux/string.h>
#include <asm/delay.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/todc.h>
static void beech_ebc_setup(void);
static void beech_fpga_setup(void);
/*
Beech board physical memory map:
Main Memory (Initialized by the BIOS)
=======================================================================
SDRAM (64 MB) 0x00000000 - 0x04000000
OPB Space: (Mapped virtual = physical in ppc4xx_setup.c)
=======================================================================
UART0 0xEF600300
UART1 0xEF600400
IIC 0xEF600500
OPB Arbiter 0xEF600600
GPIO Controller 0xEF600700
CODEC Interface 0xEF600900
Touch Panel Controller 0xEF600A00
DES Controller 0xEF600B00
EBC Space: (Mapped virtual = physical in ppc4xx_map_io(); EBC setup
for PCMCIA left to 4xx_pccf)
Space EBC Bank Physical Addresses EBC Base Address
=========================================================================
PCMCIA (32 MB) x F0000000 - F1FFFFFF F0000000
Expansion 2 F8000000 - F8FFFFFF F8000000
Linux Flash (16 MB) F9000000 - F9FFFFFF
NVRAM (32 KB) 1 FFE00000 - FFE07FFF FFE00000
Ethernet(I/O) 1 FFE20300 - FFE2030F FFE00000
(MEM) FFE40000 - FFE40FFF
FPGA_REG_4 1 FFE60000 - FFE60000 FFE00000
FPGA_REG_0 1 FFE80000 - FFE80000 FFE00000
FPGA_REG_1 1 FFEA0000 - FFEA0000 FFE00000
FPGA_REG_2 1 FFEC0000 - FFEC0000 FFE00000
FPGA_REG_3 1 FFEE0000 - FFEE0000 FFE00000
SRAM (512 KB) 0 FFF00000 - FFF7FFFF FFF00000
Boot Flash (512 KB) 0 FFF80000 - FFFFFFFF FFF00000
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
NB: On Beech 1, address ranges for Bank 2 were reversed
*/
void __init
beech_setup_arch(void)
{
ppc4xx_setup_arch();
TODC_INIT(TODC_TYPE_DCR146818, NULL, NULL, NULL, 8);
/* Set up Beech FPGA. */
beech_fpga_setup();
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
ppc4xx_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = beech_setup_arch;
#ifdef CONFIG_PPC_RTC
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_dcr146818_read_val;
ppc_md.nvram_write_val = todc_dcr146818_write_val;
#endif
/* Disable the LCD controller, which may have been left on by the
BIOS. Then do initialization of the EBC. */
mtdcri(DCRN_LCD0, DER, 0);
beech_ebc_setup();
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Non-standard board support follows
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/****************************************************************************
* EBC Setup
****************************************************************************/
/* The EBC is set up for Beech. This may simply replicate the setup already
done by the IBM BIOS for Beech (possibly with some address map changes), or
may be the first initialization if the board is booting from another BIOS.
Virtually all that is required to boot Linux on Beech is that the BIOS
enable the memory controller, load a Linux image from flash, and run it.
For optimal dynamic frequency scaling the EBC settings will also vary as the
frequency varies.
*/
static void __init
beech_ebc_setup(void)
{
ebc0_bnap_t ap;
ebc0_bncr_t cr;
/* Set EBC bank 0 for the SRAM and boot flash.
Access parameters assume 120ns AMD flash @ 66.66 MHz maximum bus
speed = 8 cycle access with 2 turnaround cycles (30 ns).
These parameters will work for the SRAM as well, which is a 70 ns
part.
NB: IBM BIOS sets this bank to burst, however bursting will never
happen in Linux because this region is mapped non-cacheable and
guarded, so it is set non-burst here. */
cr.reg = (BEECH_BANK0_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK0_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_16;
mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;
ap.fields.twt = 8;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(0), ap.reg);
/* EBC bank 1 is used for many purposes: NVRAM, Ethernet, and FPGA
registers. This is a 1 MB, 16-bit bank. The access parameters must
handle the worst case of all of the devices.
The Ethernet chip needs 20 ns setup of the addresses to the I/O
write signal (generated from the chip select), a minimum 150 ns
cycle, and 30 ns of turnaround. These settings will work for the
other devices as well.
*/
cr.reg = (BEECH_BANK1_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(1)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK1_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_16;
mtdcri(DCRN_EBC0, BnCR(1), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(1)) & EBC0_BnAP_MASK;
ap.fields.twt = 10;
ap.fields.csn = 2;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(1), ap.reg);
/* Set EBC bank 2 for the big (Linux) flash. There is 16 MB of flash,
but the CPLD decodes a 32 MB region.
Access parameters assume 90ns AMD flash @ 66.66 MHz maximum bus
speed = 6 cycle access with 2 turnaround cycles (30 ns).
NB: IBM BIOS sets this bank to burst, however bursting will never
happen in Linux because this region is mapped non-cacheable and
guarded, so it is set non-burst here. */
cr.reg = (BEECH_BANK2_PADDR & 0xfff00000) |
(mfdcri(DCRN_EBC0, BnCR(2)) & EBC0_BnCR_MASK);
cr.fields.bs = BEECH_BANK2_EBC_SIZE;
cr.fields.bu = EBC0_BnCR_BU_RW;
cr.fields.bw = EBC0_BnCR_BW_8;
mtdcri(DCRN_EBC0, BnCR(2), cr.reg);
ap.reg = mfdcri(DCRN_EBC0, BnAP(2)) & EBC0_BnAP_MASK;
ap.fields.twt = 6;
ap.fields.th = 2;
mtdcri(DCRN_EBC0, BnAP(2), ap.reg);
}
/****************************************************************************
* FPGA Setup
****************************************************************************/
/* The Beech FPGA is set up for Linux. */
static void __init
beech_fpga_setup(void)
{
volatile u8 *fpga_reg_2;
fpga_reg_2 = (volatile u8 *)
ioremap(BEECH_FPGA_REG_2_PADDR, BEECH_FPGA_REG_2_SIZE);
/* Set RTS/CTS mode for UART 1 */
*fpga_reg_2 |= FPGA_REG_2_DEFAULT_UART1_N;
}
/*
* Local variables:
* c-basic-offset: 8
* End:
*/
arch/ppc/platforms/4xx/beech.h deleted 100755 → 0
View file @ cd0e8af5
/*
* include/asm-ppc/platforms/beech.h Platform definitions for the IBM Beech
* board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved.
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*
*/
#ifdef __KERNEL__
#ifndef __ASM_BEECH_H__
#define __ASM_BEECH_H__
#include <platforms/4xx/ibm405lp.h>
#ifndef __ASSEMBLY__
/*
* Data structure defining board information maintained by the standard boot
* ROM on the IBM Beech board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
* structures.
*/
typedef struct board_info {
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned long bi_tbfreq; /* Frequency of SysTmrClk */
unsigned char bi_r_version[30]; /* Version of the IBM ROM */
unsigned int bi_memsize; /* DRAM installed, in bytes */
unsigned long sysclock_period; /* SysClk period in ns */
unsigned long sys_speed; /* SysCLk frequency in Hz */
unsigned long bi_intfreq; /* Processor speed, in Hz */
unsigned long vco_speed; /* PLL VCO speed, in Hz */
unsigned long bi_busfreq; /* PLB Bus speed, in Hz */
unsigned long opb_speed; /* OPB Bus speed, in Hz */
unsigned long ebc_speed; /* EBC Bus speed, in Hz */
} bd_t;
/* See beech.c for a concise diagram of the Beech physical memory map. */
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
/* EBC Bank 0 controls the boot flash and SRAM */
#define BEECH_BANK0_PADDR ((uint)0xfff00000)
#define BEECH_BANK0_EBC_SIZE EBC0_BnCR_BS_1MB
#define BEECH_SRAM_PADDR BEECH_BANK0_PADDR
#define BEECH_SRAM_SIZE ((uint)(512 * 1024))
#define BEECH_BOOTFLASH_PADDR (BEECH_BANK0_PADDR + (512 * 1024))
#define BEECH_BOOTFLASH_SIZE ((uint)(512 * 1024))
/* EBC bank 1 controls the NVRAM, Ethernet and CPLD registers. The different
areas are mapped in as small an area as possible to help catch any kernel
addressing errors.
NVRAM is improperly connected on Beech Pass 1. Only every other location is
accessible. This is a 32 KB NVRAM.
The Ethernet chip maps 13 address lines. We only map the "I/O" space used by
the current driver.
The FPGA "registers" are decoded on 128 KB boundarys. Each is mapped in a
separate page. */
#define BEECH_BANK1_PADDR ((uint)0xffe00000)
#define BEECH_BANK1_EBC_SIZE EBC0_BnCR_BS_1MB
#define BEECH_NVRAM_PADDR BEECH_BANK1_PADDR
#define BEECH_NVRAM_SIZE ((uint) (32 * 1024))
#define BEECH_ETHERNET_PADDR (BEECH_BANK1_PADDR + 0x00020000)
#define BEECH_ETHERNET_SIZE ((uint) (8 * 1024))
#define BEECH_FPGA_REG_0_PADDR (BEECH_BANK1_PADDR + 0x00080000)
#define BEECH_FPGA_REG_0_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_1_PADDR (BEECH_BANK1_PADDR + 0x000A0000)
#define BEECH_FPGA_REG_1_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_2_PADDR (BEECH_BANK1_PADDR + 0x000C0000)
#define BEECH_FPGA_REG_2_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_3_PADDR (BEECH_BANK1_PADDR + 0x000E0000)
#define BEECH_FPGA_REG_3_SIZE PAGE_SIZE
#define BEECH_FPGA_REG_4_PADDR (BEECH_BANK1_PADDR + 0x00060000)
#define BEECH_FPGA_REG_4_SIZE PAGE_SIZE
/* FPGA Register Bits (From IBM BIOS) [ May not be valid for Beech Pass 1 ]*/
#define FPGA_REG_0_FLASH_N 0x01
#define FPGA_REG_0_FLASH_ONBD_N 0x02
#define FPGA_REG_0_HITA_TOSH_N 0x04 /* New in Pass 2 */
#define FPGA_REG_0_STAT_OC 0x20
#define FPGA_REG_0_AC_SOURCE_SEL_N 0x40
#define FPGA_REG_0_AC_ACTIVE_N 0x80
#define FPGA_REG_1_USB_ACTIVE 0x01 /* New in Pass 2 */
#define FPGA_REG_1_CLK_VARIABLE 0x02
#define FPGA_REG_1_CLK_TEST 0x04
#define FPGA_REG_1_CLK_SS 0x08
#define FPGA_REG_1_EXT_IRQ_N 0x10
#define FPGA_REG_1_SMI_MODE_N 0x20
#define FPGA_REG_1_BATT_LOW_N 0x40
#define FPGA_REG_1_PCMCIA_PWR_FAULT_N 0x80
#define FPGA_REG_2_DEFAULT_UART1_N 0x01
#define FPGA_REG_2_EN_1_8V_PLL_N 0x02
#define FPGA_REG_2_PC_BUF_EN_N 0x08
#define FPGA_REG_2_CODEC_RESET_N 0x10 /* New in Pass 2 */
#define FPGA_REG_2_TP_JSTICK_N 0x20 /* New in Pass 2 */
#define FPGA_REG_3_GAS_GAUGE_IO 0x01
#define FPGA_REG_4_SDRAM_CLK3_ENAB 0x01
#define FPGA_REG_4_SDRAM_CLK2_ENAB 0x02
#define FPGA_REG_4_SDRAM_CLK1_ENAB 0x04
#define FPGA_REG_4_SDRAM_CLK0_ENAB 0x08
#define FPGA_REG_4_PCMCIA_5V 0x10 /* New in Pass 2 */
#define FPGA_REG_4_IRQ3 0x20 /* New in Pass 2 */
/* EBC Bank 2 contains the 16 MB "Linux" flash. The FPGA decodes a 32 MB
bank. The lower 16 MB are available for expansion devices. The upper 16 MB
are used for the "Linux" flash.
Partitioning information is for the benefit of the MTD driver. See
drivers/mtd/maps/ibm4xx.c. We currently allocate the lower 1 MB for a
kernel, and the other 15 MB for a filesystem.
*/
/* Bank 2 mappings changed between Beech Pass 1 and Pass 2 */
#ifdef CONFIG_BEECH_PASS1
#define BEECH_BIGFLASH_OFFSET 0
#else
#define BEECH_BIGFLASH_OFFSET (16 * 1024 * 1024)
#endif
#define BEECH_BANK2_PADDR ((uint)0xf8000000)
#define BEECH_BANK2_EBC_SIZE EBC0_BnCR_BS_32MB
#define BEECH_BIGFLASH_PADDR (BEECH_BANK2_PADDR + BEECH_BIGFLASH_OFFSET)
#define BEECH_BIGFLASH_SIZE (16 * 1024 * 1024)
#define BEECH_KERNEL_OFFSET 0
#define BEECH_KERNEL_SIZE (1 * 1024 * 1024)
#define BEECH_FREE_AREA_OFFSET BEECH_KERNEL_SIZE
#define BEECH_FREE_AREA_SIZE (BEECH_BIGFLASH_SIZE - BEECH_KERNEL_SIZE)
/* The PCMCIA controller driver 4xx_pccf.c is responsible for the EBC setup of
PCMCIA. Externally, EBC bank selects 3..7 take on PCMCIA functions when
PCMCIA is enabled. */
#define BEECH_PCMCIA_PADDR ((uint)0xf0000000)
#define BEECH_PCMCIA_SIZE ((uint)(32 * 1024 * 1024))
/* We do not currently support the internal clock mode for the UART. This
limits the minimum OPB frequency to just over 2X the UART oscillator
frequency. At OPB frequencies less than this the serial port will not
function due to the way that SerClk is sampled. */
#define PPC4xx_SERCLK_FREQ 11059200
#define BASE_BAUD (PPC4xx_SERCLK_FREQ / 16)
#define PPC4xx_MACHINE_NAME "IBM 405LP Beech"
/****************************************************************************
* Non-standard board support follows
****************************************************************************/
extern int beech_sram_free(void *p);
extern int ibm405lp_set_pixclk(unsigned pixclk_low, unsigned pixclk_high);
extern void *beech_sram_alloc(size_t size);
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_BEECH_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/cedar.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/cedar.c
*
* Support for the IBM NP405L ceder eval board
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/todc.h>
void *cedar_rtc_base;
void __init
cedar_setup_arch(void)
{
bd_t *bip = &__res;
/* RTC step for the walnut */
cedar_rtc_base = (void *) CEDAR_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, cedar_rtc_base, cedar_rtc_base,
cedar_rtc_base, 8);
#ifdef CONFIG_DEBUG_BRINGUP
printk("\n");
printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
printk("\n");
printk("bi_s_version\t %s\n", bip->bi_s_version);
printk("bi_r_version\t %s\n", bip->bi_r_version);
printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
bip->bi_memsize / (1024 * 1000));
printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
bip->bi_enetaddr[0][0], bip->bi_enetaddr[0][1],
bip->bi_enetaddr[0][2], bip->bi_enetaddr[0][3],
bip->bi_enetaddr[0][4], bip->bi_enetaddr[0][5]);
printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 1,
bip->bi_enetaddr[1][0], bip->bi_enetaddr[1][1],
bip->bi_enetaddr[1][2], bip->bi_enetaddr[1][3],
bip->bi_enetaddr[1][4], bip->bi_enetaddr[1][5]);
printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
bip->bi_intfreq, bip->bi_intfreq / 1000000);
printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
bip->bi_busfreq, bip->bi_busfreq / 1000000);
printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
printk("\n");
#endif
/* Identify the system */
printk
("IBM Cedar port (C) 2002 MontaVista Software, Inc. (source@mvista.com)\n");
}
void __init
cedar_map_io(void)
{
ppc4xx_map_io();
io_block_mapping(CEDAR_RTC_VADDR,
CEDAR_RTC_PADDR, CEDAR_RTC_SIZE, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
ppc4xx_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = cedar_setup_arch;
ppc_md.setup_io_mappings = cedar_map_io;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
}
arch/ppc/platforms/4xx/cedar.h deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/cedar.h
*
* Macros, definitions, and data structures specific to the IBM PowerPC
* Cedar eval board.
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2000 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_CEDAR_H__
#define __ASM_CEDAR_H__
#include <platforms/4xx/ibmnp405l.h>
#ifndef __ASSEMBLY__
/*
* Data structure defining board information maintained by the boot
* ROM on IBM's "Cedar" evaluation board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
* structures.
*/
typedef struct board_info {
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[30]; /* Version of the IBM ROM */
unsigned int bi_memsize; /* DRAM installed, in bytes */
unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */
unsigned char bi_pci_mac[6];
unsigned int bi_intfreq; /* Processor speed, in Hz */
unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI speed in Hz */
} bd_t;
/* Some 4xx parts use a different timebase frequency from the internal clock.
*/
#define bi_tbfreq bi_intfreq
/* Memory map for the IBM "Cedar" NP405 evaluation board.
*/
extern void *cedar_rtc_base;
#define CEDAR_RTC_PADDR ((uint)0xf0000000)
#define CEDAR_RTC_VADDR CEDAR_RTC_PADDR
#define CEDAR_RTC_SIZE ((uint)8*1024)
/* Early initialization address mapping for block_io.
* Standard 405GP map.
*/
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
#define BASE_BAUD 201600
#else
#define BASE_BAUD 691200
#endif
#define PPC4xx_MACHINE_NAME "IBM NP405L Cedar"
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_CEDAR_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/ibm405lp.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/ibm405lp.c 405LP-specific code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved.
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*/
#include <linux/config.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <asm/delay.h>
#include <asm/hardirq.h>
#include <asm/ibm4xx.h>
#include <asm/machdep.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/uaccess.h>
#include <asm/ocp.h>
struct ocp_def core_ocp[] __initdata = {
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
#ifdef CONFIG_PM
/* Set up the 405LP clock and power management unit for aggressive power
management.
Briefly, there are 3 CPM "classes":
Class 1 - Either completely asleep or awake. The "force" state is
equivalent to the "enabled" state. Many Class 1 units are
critical system components and are never power managed.
Class 2 - Can be enabled for power management, where sleep requests are
made by the peripheral, typically after an inactivity timeout.
When sleeping, critical interfaces remain active, and
awaken the unit whenever it is targeted with a transaction.
Class 3 - Can be enabled for power management, where sleep requests are
made by the CPM. Power management for these units typically
will require intelligence in a device driver.
In the current implementation, the "force" bits are only used on Class 1
devices, and only when the associated driver has the intelligence necessary
to "unforce" the power management state. A previous scheme, which tried to
enable power management based on whether a particular driver was compiled
with the kernel, caused many problems and is never used here.
Class 2 devices with timeouts are normally initialized for the most
aggressive values. There is no power management benefit of "forcing" Class
2 devices over letting their inactivity timeouts take effect. Therefore,
after being set up here, Class 2 device drivers don't need to worry about
CPM.
No Class 3 devices are handled yet. */
void __init
ibm405lp_setup_cpm(void)
{
u32 force = 0;
u32 enable = 0;
dma0_slp_t dma0_slp;
dcp0_cfg_t dcp0_cfg;
ebc0_cfg_t ebc0_cfg;
sdram0_cfg_t sdram0_cfg;
sdram0_pmit_t sdram0_pmit;
sla0_slpmd_t sla0_slpmd;
/* Initialize the CPM state */
mtdcr(DCRN_CPMFR, force);
mtdcr(DCRN_CPMER, enable);
/* IIC - Class 3 - Not handled yet. The driver should at least be able
to force/unforce itself. */
/* CPU - class 2 - There doesn't appear to be a timeout associated with
this, and the exact function is not documented anywhere. It saves a
lot of power, though. I assume this gates core clocks when the CPU
core is asleep, and probably adds a couple of cycles of latency when
the CPU core wakes up. */
enable |= IBM_CPM_CPU;
/* DMA - class 2. Set for the minimum timeout, which is 32 cycles. */
dma0_slp.reg = mfdcr(DCRN_SLP);
dma0_slp.fields.sme = 1;
dma0_slp.fields.idu = 0;
mtdcr(DCRN_SLP, dma0_slp.reg);
enable |= IBM_CPM_DMA;
/* BRG - Class 2. Seems to crash the system when enabled in 405LP Pass
1
DCP (CodePack) - Class 2. The semantics of the sleep delay are not
documented. We'll use 32 (what the heck). */
dcp0_cfg.reg = mfdcri(DCRN_DCP0, CFG);
dcp0_cfg.fields.slen = 1;
dcp0_cfg.fields.sldy = 32;
mtdcri(DCRN_DCP0, CFG, dcp0_cfg.reg);
enable |= IBM_CPM_DCP;
/* EBC - Class 2. Set for minimum timeout, which is 32 cycles. [ I
think this is 32. It may be 64. I don't trust the documentation. ]
*/
ebc0_cfg.reg = mfdcri(DCRN_EBC0, CFG);
ebc0_cfg.fields.pme = 1;
ebc0_cfg.fields.pmt = 1;
mtdcri(DCRN_EBC0, CFG, ebc0_cfg.reg);
enable |= IBM_CPM_EBC;
/* SDRAM - Class 2. Set for the minimum 32-cycle timeout.
The documentation on this core is clear - waking a sleeping SDRAM
controller takes 2 PLB cycles, which is added to the latency of the
memory operation. If someone can prove that this is affecting
performance we can easily back this off. */
sdram0_cfg.reg = mfdcri(DCRN_SDRAM0, CFG);
sdram0_cfg.fields.pme = 1;
mtdcri(DCRN_SDRAM0, CFG, sdram0_cfg.reg);
sdram0_pmit.reg = mfdcri(DCRN_SDRAM0, PMIT);
sdram0_pmit.fields.cnt = 0;
mtdcri(DCRN_SDRAM0, PMIT, sdram0_pmit.reg);
enable |= IBM_CPM_SDRAM0;
/* PLB - Class 2. Seems to crash the system when enabled in 405LP Pass
1.
GPIO - Class 1. This unit is used for many things, and no single
driver controls all GPIO. It's best left unmanaged (it doesn't use
much power anyway). NB: 405LP Pass 1 erratum - forcing PM on GPIO
kills the TPC.
UART0 - Class 1
UART1 - Class 1
Someone should work on the serial port drivers to enable PM support
for them. Any takers?
UIC - Class 1
CPU_TMRCLK - Class 1
These system resources are never power managed. */
/* SLA - Class 2. Set for the minimum 32-cycle timeout. */
sla0_slpmd.reg = mfdcri(DCRN_SLA0, SLPMD);
sla0_slpmd.fields.slen = 1;
sla0_slpmd.fields.slcr = 0;
mtdcri(DCRN_SLA0, SLPMD, sla0_slpmd.reg);
enable |= IBM_CPM_SLA;
/* CSI - Class 1.
TPC - Class 1.
TDES - Class 1.
The drivers for these units are power-aware, and manage the device
properly. By default these units are forced off at boot. */
force |= IBM_CPM_CSI;
force |= IBM_CPM_TPC;
force |= IBM_CPM_TDES;
/* Set the CPM state */
mtdcr(DCRN_CPMFR, force);
mtdcr(DCRN_CPMER, enable);
}
#endif
/* This routine is included here because the framebuffer driver needs a way to
tell the system the Pixel clock frequency it needs, regardless of whether
run-time frequency scaling is configured. A hook and a couple of global
variables are always present and will be used by the RTVFS driver if it is
loaded.
Pixel clock setting is kind of a hack, as the frequency steps available from
the PLB/PixClk divider may be too large to guarantee that we'll hit within
the given limits. We never set the frequency above the upper bound, but due
to quantization may need to set the frequency below the lower bound. So far
it works OK for the panels we've tried.
In general, the choice of a system clock frequency should be made with
consideration of the LCD panel to be attached, to guarantee a good clock
divider for the Pixel clock regardless of frequency scaling.
Clock frequencies are in KHz. If pixclk_min or pixclk_max are zero, we set
the lowest possible frequency to conserve energy. */
int (*set_pixclk_hook) (unsigned pixclk_min, unsigned pixclk_max) = NULL;
unsigned last_pixclk_min = 0;
unsigned last_pixclk_max = 0;
EXPORT_SYMBOL(set_pixclk_hook);
EXPORT_SYMBOL(last_pixclk_min);
EXPORT_SYMBOL(last_pixclk_max);
int
ibm405lp_set_pixclk(unsigned pixclk_min, unsigned pixclk_max)
{
unsigned divider;
bd_t *bip = (bd_t *) __res;
unsigned plb_khz = bip->bi_busfreq / 1000;
cpc0_cgcr1_t cgcr1;
if (set_pixclk_hook) {
return (set_pixclk_hook) (pixclk_min, pixclk_max);
} else {
if ((pixclk_min == 0) || (pixclk_max == 0))
divider = CPC0_DIV_MAX;
else {
divider = plb_khz / pixclk_min;
if (divider == 0)
divider = 1;
if ((divider < CPC0_DIV_MAX) &&
((plb_khz / divider) > pixclk_max))
divider++;
}
cgcr1.reg = mfdcr(DCRN_CPC0_CGCR1);
cgcr1.fields.ppxl = CPC0_DIV_ENCODE(divider);
mtdcr(DCRN_CPC0_CGCR1, cgcr1.reg);
last_pixclk_min = pixclk_min;
last_pixclk_max = pixclk_max;
return 0;
}
}
arch/ppc/platforms/4xx/ibm405lp.h deleted 100644 → 0
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arch/ppc/platforms/4xx/ibmnp405l.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmnp405l.c
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/param.h>
#include <linux/string.h>
#include <platforms/4xx/ibmnp405l.h>
struct ocp_def core_ocp[] = {
{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
{UART, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OPB, OPB0_BASE, OCP_IRQ_NA, IBM_CPM_OPB},
{EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
{EMAC, EMAC1_BASE, BL_MAC_ETH1, IBM_CPM_EMAC1},
{ZMII, ZMII0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibmnp405l.h deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmnp405l.h
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBMNP405L_H__
#define __ASM_IBMNP405L_H__
#include <linux/config.h>
/* serial port defines */
#define RS_TABLE_SIZE 2
#define UART0_INT 0
#define UART1_INT 1
#define UART0_IO_BASE 0xEF600300
#define UART1_IO_BASE 0xEF600400
#define IIC0_BASE 0xEF600500
#define OPB0_BASE 0xEF600600
#define GPIO0_BASE 0xEF600700
#define EMAC0_BASE 0xEF600800
#define EMAC1_BASE 0xEF600900
#define ZMII0_BASE 0xEF600C10
#define BL_MAC_WOL 41 /* WOL */
#define BL_MAL_SERR 45 /* MAL SERR */
#define BL_MAL_TXDE 46 /* MAL TXDE */
#define BL_MAL_RXDE 47 /* MAL RXDE */
#define BL_MAL_TXEOB 17 /* MAL TX EOB */
#define BL_MAL_RXEOB 18 /* MAL RX EOB */
#define BL_MAC_ETH0 37 /* MAC */
#define BL_MAC_ETH1 38 /* MAC */
#define EMAC_NUMS 2
#define IIC0_IRQ 2
#undef NR_UICS
#define NR_UICS 2
#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
iomem_base:(u8 *) UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(0) \
STD_UART_OP(1)
#endif
#if defined(CONFIG_UART0_TTYS1)
#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(1) \
STD_UART_OP(0)
#endif
/* DCR defines */
/* ------------------------------------------------------------------------- */
#define DCRN_CHCR_BASE 0x0F1
#define DCRN_CHPSR_BASE 0x0B4
#define DCRN_CPMSR_BASE 0x0BA
#define DCRN_CPMFR_BASE 0x0B9
#define DCRN_CPMER_BASE 0x0B8
#define IBM_CPM_EMAC0 0x00800000 /* on-chip ethernet MM unit */
#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
#define IBM_CPM_CPU 0x00008000 /* processor core */
#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
#define IBM_CPM_HDLC 0x00000800 /* HDCL */
#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
#define IBM_CPM_DMA 0x00000040 /* DMA controller */
#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
| IBM_CPM_EMAC0 | IBM_CPM_EMAC1)
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRN_DMA3_BASE 0x118
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_DMASR_BASE 0x120
#define DCRN_EBC_BASE 0x012
#define DCRN_DCP0_BASE 0x014
#define DCRN_MAL_BASE 0x180
#define DCRN_MAL1_BASE 0x200
#define DCRN_OCM0_BASE 0x018
#define DCRN_PLB0_BASE 0x084
#define DCRN_PLLMR_BASE 0x0F0
#define DCRN_POB0_BASE 0x0A0
#define DCRN_SDRAM0_BASE 0x010
#define DCRN_UIC0_BASE 0x0C0
#define DCRN_UIC1_BASE 0x0D0
#define DCRN_CPC0_EPRCSR 0x0F3
#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
#define CHR1_CETE 0x00000004 /* CPU external timer enable */
#define UIC0 DCRN_UIC0_BASE
#define UIC1 DCRN_UIC1_BASE
#define SDRAM_CFG 0x20
#define SDRAM0_ECCCFG 0x94
#define SDRAM_NO_ECC 0x10000000
#include <asm/ibm405.h>
#endif /* __ASM_IBMNP405L_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/ibmnp4gs.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmnp4gs.c
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/init.h>
#include "ibmnp4gs.h"
#include <asm/ocp.h>
struct ocp_def core_ocp[] = {
{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
{PCI, PCIL0_BASE, OCP_IRQ_NA, IBM_CPM_PCI},
{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibmnp4gs.h deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmnp4gs.h
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBMNP4GS_H__
#define __ASM_IBMNP4GS_H__
#include <linux/config.h>
#include <asm/ibm_ocp.h>
/* ibm405.h at bottom of this file */
/* PCI
* PCI Bridge config reg definitions
* see 17-19 of manual
*/
#define PPC405_PCI_CONFIG_ADDR 0xeec00000
#define PPC405_PCI_CONFIG_DATA 0xeec00004
#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
/* setbat */
#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define PCI_CONFIG_ADDR_MASK 0x7F000000
#define PCI_CONFIG_CYCLE_ENABLE 0x80000000
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
#define PCI_CONFIG_ADDR_MASK 0x7F000000
#define PCI_CONFIG_CYCLE_ENABLE 0x80000000
#define PCI_BASE_ADDRESS_MEM_CARD1 0x80000000
#define PCI_BASE_ADDRESS_MEM_CARD2 0x90000000
#define PPC405_UART0_INT 1
#define PPC_405RAINIER2_IO_PAGE ((void*)0xe8001000)
#define PPC_405RAINIER1_IO_PAGE ((void*)0xe8002000)
#define PPC405_UART0_IO_BASE 0x300 /* mostly use (rainier_io_page+0x300) */
#define RAINIER_IO_PAGE_INTERPOSER_PADDR 0xe8000000
#define RAINIER_IO_PAGE_INTERPOSER_VADDR RAINIER_IO_PAGE_INTERPOSER_PADDR
#define RAINIER_IO_PAGE_PCI_PADDR 0xeec00000
#define RAINIER_IO_PAGE_PCI_VADDR RAINIER_IO_PAGE_PCI_PADDR
/* serial port defines */
#define RS_TABLE_SIZE 1
#define UART0_INT 1
#define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE PPC_405RAINIER1_IO_PAGE + PPC405_UART0_IO_BASE
#define UART_NUMS 1
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
iomem_base: (u8 *)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_PORT_DFNS \
STD_UART_OP(0)
#endif
/* DCR defines */
#define DCRN_CHCR_BASE 0x0B1
#define DCRN_CHPSR_BASE 0x0B4
#define DCRN_CPMSR_BASE 0x0B8
#define DCRN_CPMFR_BASE 0x0BA
#define PSR_PLL_FWD_MASK 0xC0000000
#define PSR_PLL_FDBACK_MASK 0x30000000
#define PSR_PLL_TUNING_MASK 0x0E000000
#define PSR_PLB_CPU_MASK 0x01800000
#define PSR_OPB_PLB_MASK 0x00600000
#define PSR_PCI_PLB_MASK 0x00180000
#define PSR_EB_PLB_MASK 0x00060000
#define PSR_ROM_WIDTH_MASK 0x00018000
#define PSR_ROM_LOC 0x00004000
#define PSR_PCI_ASYNC_EN 0x00001000
#define PSR_PCI_ARBIT_EN 0x00000400
#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
#define IBM_CPM_CPU 0x20000000 /* processor core */
#define IBM_CPM_DMA 0x10000000 /* DMA controller */
#define IBM_CPM_BRG 0x08000000 /* PLB to OPB bridge */
#define IBM_CPM_DCP 0x04000000 /* CodePack */
#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
#define DFLT_IBM4xx_PM 0
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRN_DMA3_BASE 0x118
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_DMASR_BASE 0x120
#define DCRN_EBC_BASE 0x012
#define DCRN_DCP0_BASE 0x014
#define DCRN_MAL_BASE 0x180
#define DCRN_OCM0_BASE 0x018
#define DCRN_PLB0_BASE 0x084
#define DCRN_PLLMR_BASE 0x0B0
#define DCRN_POB0_BASE 0x0A0
#define DCRN_SDRAM0_BASE 0x010
#define DCRN_UIC0_BASE 0x0C0
#define UIC0 DCRN_UIC0_BASE
#include <asm/ibm405.h>
#endif /* __ASM_IBMNP4GS_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/ibmstb3.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmstb3.c
*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include "ibmstb3.h"
#include <asm/ocp.h>
struct ocp_def core_ocp[] = {
{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{IIC, IIC1_BASE, IIC1_IRQ, IBM_CPM_IIC1},
{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibmstb3.h deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/ibmstb3.h
*
* Authors: Armin Kuster <akuster@mvista.com>, Tom Rini <trini@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBMSTBX_H__
#define __ASM_IBMSTBX_H__
#include <linux/config.h>
#include <platforms/4xx/ibm_ocp.h>
/* ibm405.h at bottom of this file */
/*
* Memory map for the IBM "Redwood-4" STB03xxx evaluation board.
*
* The STB03xxx internal i/o addresses don't work for us 1:1,
* so we need to map them at a well know virtual address.
*
* 4000 000x uart1 -> 0xe000 000x
* 4001 00xx ppu
* 4002 00xx smart card
* 4003 000x iic
* 4004 000x uart0
* 4005 0xxx timer
* 4006 00xx gpio
* 4007 00xx smart card
* 400b 000x iic
* 400c 000x scp
* 400d 000x modem
*/
#define STB03xxx_IO_BASE ((uint)0xe0000000)
#define PPC4xx_ONB_IO_PADDR ((uint)0x40000000)
#define PPC4xx_ONB_IO_VADDR STB03xxx_IO_BASE
#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
/* Since we're into address mapping hacks, at least try to hide
* it under a macro.....
*/
#define STB03xxx_MAP_IO_ADDR(a) (((uint)(a) & 0x000fffff) + PPC4xx_ONB_IO_VADDR)
#define RS_TABLE_SIZE 1
#define UART0_INT 20
#ifdef __BOOTER__
#define UART0_IO_BASE 0x40040000
#else
#define UART0_IO_BASE 0xe0040000
#endif
/* UART 0 is duped here so when the SICC is the default console
* then ttys1 is configured properly - armin
*/
#define UART1_INT 20
#ifdef __BOOTER__
#define UART1_IO_BASE 0x40040000
#else
#define UART1_IO_BASE 0xe0040000
#endif
/* need to make this work in scheme - armin */
#define SICC0_INTRX 21
#define SICC0_INTTX 22
#define SICC0_IO_BASE ((uint* )0x40000000)
#define IDE0_BASE 0xf2100000
#define REDWOOD_IDE_CTRL 0xf4100000
#define IIC0_BASE 0x40030000
#define IIC1_BASE 0x400b0000
#define OPB0_BASE 0x40010000
#define GPIO0_BASE 0x40060000
#define IIC0_IRQ 9
#define IIC1_IRQ 10
#define IIC_OWN 0x55
#define IIC_CLOCK 50
#define IDE0_IRQ 25
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
iomem_base: (u8 *)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(0)
#endif
#if defined(CONFIG_UART0_TTYS1)
#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(1)
#endif
/* ------------------------------------------------------------------------- */
#define DCRN_DCRX_BASE 0x020
#define DCRN_CIC_BASE 0x030
#define DCRN_UIC0_BASE 0x040
#define DCRN_PLB0_BASE 0x054
#define DCRN_PLB1_BASE 0x064
#define DCRN_EBIMC_BASE 0x070
#define DCRN_POB0_BASE 0x0B0
#define DCRN_BE_BASE 0x090
#define DCRN_DMA0_BASE 0x0C0
#define DCRN_DMA1_BASE 0x0C8
#define DCRN_DMA2_BASE 0x0D0
#define DCRN_DMA3_BASE 0x0D8
#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
#define DCRN_DMASR_BASE 0x0E0
#define DCRN_CPMFR_BASE 0x102
#define DCRN_SCCR_BASE 0x120
#define UIC0 DCRN_UIC0_BASE
#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
#define IBM_CPM_I1284 0x40000000 /* IEEE-1284 */
#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
#define IBM_CPM_DMA 0x01000000 /* DMA controller */
#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
#define IBM_CPM_DCRX 0x00040000 /* DCR Extension */
#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM 0 memory controller */
#define IBM_CPM_XPT54 0x00002000 /* Transport - 54 Mhz */
#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
#define IBM_CPM_MSI 0x00000010 /* Modem Serial Interface (SSP) */
#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
#define IBM_CPM_DSCR 0x00000004 /* Descrambler */
#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
| IBM_CPM_DMA | IBM_CPM_CBS | IBM_CPM_SDRAM0 \
| IBM_CPM_XPT54 | IBM_CPM_TMRCLK | IBM_CPM_XPT27 \
| IBM_CPM_UIC)
#ifdef DCRN_CIC_BASE
#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
#endif
#ifdef DCRN_DCRX_BASE
#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
#endif
#ifdef DCRN_EBC_BASE
#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */
#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */
#endif
#ifdef DCRN_EBIMC_BASE
#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
#endif
#ifdef DCRN_SCCR_BASE
#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0)
#endif
#ifdef DCRN_SDRAM0_BASE
#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
#endif
#ifdef DCRN_OCM0_BASE
#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
#endif
#include <asm/ibm405.h>
#endif /* __ASM_IBMSTBX_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/oak_setup.c → arch/ppc/platforms/4xx/oak.c
View file @ f6eb8139
......@@ -2,7 +2,7 @@
*
* Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
*
* Module name: oak_setup.c
* Module name: oak.c
*
* Description:
* Architecture- / platform-specific boot-time initialization code for
......@@ -29,7 +29,7 @@
#include <asm/ppc4xx_pic.h>
#include <asm/time.h>
#include "oak_setup.h"
#include "oak.h"
/* Function Prototypes */
......
arch/ppc/platforms/4xx/oak.h
View file @ f6eb8139
......@@ -60,6 +60,31 @@ typedef struct board_info {
unsigned int bi_busfreq; /* Bus speed, in Hz */
} bd_t;
#ifdef __cplusplus
extern "C" {
#endif
extern void oak_init(unsigned long r3,
unsigned long ird_start,
unsigned long ird_end,
unsigned long cline_start,
unsigned long cline_end);
extern void oak_setup_arch(void);
extern int oak_setup_residual(char *buffer);
extern void oak_init_IRQ(void);
extern int oak_get_irq(struct pt_regs *regs);
extern void oak_restart(char *cmd);
extern void oak_power_off(void);
extern void oak_halt(void);
extern void oak_time_init(void);
extern int oak_set_rtc_time(unsigned long now);
extern unsigned long oak_get_rtc_time(void);
extern void oak_calibrate_decr(void);
#ifdef __cplusplus
}
#endif
/* Some 4xx parts use a different timebase frequency from the internal clock.
*/
#define bi_tbfreq bi_intfreq
......
arch/ppc/platforms/4xx/redwood.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/redwood.c
*
* Author: Frank Rowand <frank_rowand@mvista.com>, or source@mvista.com
*
* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <asm/pgtable.h>
#include <asm/ibm4xx.h>
#include <asm/io.h>
#include <asm/machdep.h>
void __init
redwood_setup_arch(void)
{
ppc4xx_setup_arch();
#ifdef CONFIG_IDE
void *xilinx, *xilinx_1, *xilinx_2;
unsigned short reg5;
xilinx = ioremap(IDE_XLINUX_MUX_BASE, 0x10);
/* init xilinx control registers - enable ide mux, clear reset bit */
if (!xilinx) {
printk(KERN_CRIT
"redwood4_setup_arch() xilinx ioremap failed\n");
return;
}
xilinx_1 = xilinx;
xilinx_2 = xilinx + 0xe;
reg5 = readw(xilinx_1);
writeb(reg5 |= ~(0x8001), xilinx_1);
writeb(0, xilinx_2);
udelay(10 * 1000);
writeb(reg5 & 0x8001, xilinx_1);
writeb(0, xilinx_2);
/* add RE & OEN to value set by boot rom */
mtdcr(DCRN_BRCR3, 0x407cfffe);
#endif
}
void __init
redwood_map_io(void)
{
int i;
ppc4xx_map_io();
io_block_mapping(OAKNET_IO_VADDR,
OAKNET_IO_PADDR, OAKNET_IO_SIZE, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
ppc4xx_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = redwood_setup_arch;
ppc_md.setup_io_mappings = redwood_map_io;
}
arch/ppc/platforms/4xx/redwood.h deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/4xx/redwood.h
*
* Macros, definitions, and data structures specific to the IBM PowerPC
* STB03xxx "Redwood" evaluation board.
*
* Author: Frank Rowand <frank_rowand@mvista.com>, or source@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_REDWOOD_H__
#define __ASM_REDWOOD_H__
/* Redwoods have an STB03xxx or STB04xxx core */
#include <platforms/4xx/ibmstb3.h>
#ifndef __ASSEMBLY__
typedef struct board_info {
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[30]; /* Version of the IBM ROM */
unsigned int bi_memsize; /* DRAM installed, in bytes */
unsigned int bi_dummy; /* field shouldn't exist */
unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
unsigned int bi_intfreq; /* Processor speed, in Hz */
unsigned int bi_busfreq; /* Bus speed, in Hz */
} bd_t;
#define bi_tbfreq bi_intfreq
#endif /* !__ASSEMBLY__ */
#define bi_tbfreq bi_intfreq
#define OAKNET_IO_PADDR ((uint)0xf2000000)
#define OAKNET_IO_VADDR OAKNET_IO_PADDR
#define OAKNET_IO_BASE OAKNET_IO_VADDR
/* ftr revisit- io size was 0xffff in old-line, is 0x40 in oak.h */
#define OAKNET_IO_SIZE 0xffff
#define OAKNET_INT 26 /* EXTINT1 */
#define IDE_XLINUX_MUX_BASE 0xf2040000
#define IDE_DMA_ADDR 0xfce00000
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#define BASE_BAUD (378000000 / 18 / 16)
#define PPC4xx_MACHINE_NAME "IBM Redwood"
#endif /* __ASM_REDWOOD_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/Makefile
View file @ f6eb8139
......@@ -20,7 +20,7 @@ obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \
pmac_feature.o pmac_pci.o pmac_sleep.o \
pmac_low_i2c.o
obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o
obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_time.o prep_setup.o
obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
ifeq ($(CONFIG_PPC_PMAC),y)
obj-$(CONFIG_NVRAM) += pmac_nvram.o
obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
......
arch/ppc/platforms/prep_setup.c
View file @ f6eb8139
......@@ -58,16 +58,14 @@
#include <asm/i8259.h>
#include <asm/open_pic.h>
#include <asm/pci-bridge.h>
#include <asm/todc.h>
TODC_ALLOC();
unsigned char ucSystemType;
unsigned char ucBoardRev;
unsigned char ucBoardRevMaj, ucBoardRevMin;
extern unsigned long mc146818_get_rtc_time(void);
extern int mc146818_set_rtc_time(unsigned long nowtime);
extern unsigned long mk48t59_get_rtc_time(void);
extern int mk48t59_set_rtc_time(unsigned long nowtime);
extern unsigned char prep_nvram_read_val(int addr);
extern void prep_nvram_write_val(int addr,
unsigned char val);
......@@ -814,12 +812,12 @@ prep_setup_arch(void)
}
/*
* Determine the decrementer frequency from the residual data
* This allows for a faster boot as we do not need to calibrate the
* decrementer against another clock. This is important for embedded systems.
* First, see if we can get this information from the residual data.
* This is important on some IBM PReP systems. If we cannot, we let the
* TODC code handle doing this.
*/
static int __init
prep_res_calibrate_decr(void)
static void __init
prep_calibrate_decr(void)
{
#ifdef CONFIG_PREP_RESIDUAL
unsigned long freq, divisor = 4;
......@@ -831,149 +829,9 @@ prep_res_calibrate_decr(void)
(freq/divisor)%1000000);
tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
tb_ticks_per_jiffy = freq / HZ / divisor;
return 0;
} else
#endif
return 1;
}
/*
* Uses the on-board timer to calibrate the on-chip decrementer register
* for prep systems. On the pmac the OF tells us what the frequency is
* but on prep we have to figure it out.
* -- Cort
*/
/* Done with 3 interrupts: the first one primes the cache and the
* 2 following ones measure the interval. The precision of the method
* is still doubtful due to the short interval sampled.
*/
static volatile int calibrate_steps __initdata = 3;
static unsigned tbstamp __initdata = 0;
static irqreturn_t __init
prep_calibrate_decr_handler(int irq, void *dev, struct pt_regs *regs)
{
unsigned long t, freq;
int step=--calibrate_steps;
t = get_tbl();
if (step > 0) {
tbstamp = t;
} else {
freq = (t - tbstamp)*HZ;
printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq/1000000, freq%1000000);
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
}
return IRQ_HANDLED;
}
static void __init
prep_calibrate_decr(void)
{
int res;
/* Try and get this from the residual data. */
res = prep_res_calibrate_decr();
/* If we didn't get it from the residual data, try this. */
if ( res ) {
#define TIMER0_COUNT 0x40
#define TIMER_CONTROL 0x43
/* set timer to periodic mode */
outb_p(0x34,TIMER_CONTROL);/* binary, mode 2, LSB/MSB, ch 0 */
/* set the clock to ~100 Hz */
outb_p(LATCH & 0xff , TIMER0_COUNT); /* LSB */
outb(LATCH >> 8 , TIMER0_COUNT); /* MSB */
if (request_irq(0, prep_calibrate_decr_handler, 0, "timer", NULL) != 0)
panic("Could not allocate timer IRQ!");
local_irq_enable();
/* wait for calibrate */
while ( calibrate_steps )
;
local_irq_disable();
free_irq( 0, NULL);
}
}
static long __init
mk48t59_init(void) {
unsigned char tmp;
tmp = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
if (tmp & MK48T59_RTC_CB_STOP) {
printk("Warning: RTC was stopped, date will be wrong.\n");
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLB,
tmp & ~MK48T59_RTC_CB_STOP);
/* Low frequency crystal oscillators may take a very long
* time to startup and stabilize. For now just ignore the
* the issue, but attempting to calibrate the decrementer
* from the RTC just after this wakeup is likely to be very
* inaccurate. Firmware should not allow to load
* the OS with the clock stopped anyway...
*/
}
/* Ensure that the clock registers are updated */
tmp = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
tmp &= ~(MK48T59_RTC_CA_READ | MK48T59_RTC_CA_WRITE);
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, tmp);
return 0;
}
/* We use the NVRAM RTC to time a second to calibrate the decrementer,
* the RTC registers have just been set up in the right state by the
* preceding routine.
*/
static void __init
mk48t59_calibrate_decr(void)
{
unsigned long freq;
unsigned long t1;
unsigned char save_control;
long i;
unsigned char sec;
/* Make sure the time is not stopped. */
save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA,
(save_control & (~MK48T59_RTC_CB_STOP)));
/* Now make sure the read bit is off so the value will change. */
save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
save_control &= ~MK48T59_RTC_CA_READ;
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, save_control);
/* Read the seconds value to see when it changes. */
sec = ppc_md.nvram_read_val(MK48T59_RTC_SECONDS);
/* Actually this is bad for precision, we should have a loop in
* which we only read the seconds counter. nvram_read_val writes
* the address bytes on every call and this takes a lot of time.
* Perhaps an nvram_wait_change method returning a time
* stamp with a loop count as parameter would be the solution.
*/
for (i = 0 ; i < 1000000 ; i++) { /* may take up to 1 second... */
t1 = get_tbl();
if (ppc_md.nvram_read_val(MK48T59_RTC_SECONDS) != sec) {
break;
}
}
sec = ppc_md.nvram_read_val(MK48T59_RTC_SECONDS);
for (i = 0 ; i < 1000000 ; i++) { /* Should take up 1 second... */
freq = get_tbl()-t1;
if (ppc_md.nvram_read_val(MK48T59_RTC_SECONDS) != sec)
break;
}
printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq/1000000, freq%1000000);
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
todc_calibrate_decr();
}
static unsigned int __prep
......@@ -1163,18 +1021,19 @@ prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.nvram_read_val = prep_nvram_read_val;
ppc_md.nvram_write_val = prep_nvram_write_val;
ppc_md.time_init = NULL;
ppc_md.time_init = todc_time_init;
if (_prep_type == _PREP_IBM) {
ppc_md.set_rtc_time = mc146818_set_rtc_time;
ppc_md.get_rtc_time = mc146818_get_rtc_time;
ppc_md.calibrate_decr = prep_calibrate_decr;
TODC_INIT(TODC_TYPE_MC146818, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
} else {
ppc_md.set_rtc_time = mk48t59_set_rtc_time;
ppc_md.get_rtc_time = mk48t59_get_rtc_time;
ppc_md.calibrate_decr = mk48t59_calibrate_decr;
ppc_md.time_init = mk48t59_init;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
}
ppc_md.calibrate_decr = prep_calibrate_decr;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.setup_io_mappings = prep_map_io;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
......
arch/ppc/platforms/prep_time.c deleted 100644 → 0
View file @ cd0e8af5
/*
* arch/ppc/platforms/prep_time.c
*
* Copyright (C) 1991, 1992, 1995 Linus Torvalds
*
* Adapted for PowerPC (PReP) by Gary Thomas
* Modified by Cort Dougan (cort@cs.nmt.edu).
* Copied and modified from arch/i386/kernel/time.c
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/bcd.h>
#include <asm/sections.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prep_nvram.h>
#include <asm/mk48t59.h>
#include <asm/time.h>
extern spinlock_t rtc_lock;
/*
* The motorola uses the m48t18 rtc (includes DS1643) whose registers
* are at a higher end of nvram (1ff8-1fff) than the ibm mc146818
* rtc (ds1386) which has regs at addr 0-d). The intel gets
* past this because the bios emulates the mc146818.
*
* Why in the world did they have to use different clocks?
*
* Right now things are hacked to check which machine we're on then
* use the appropriate macro. This is very very ugly and I should
* probably have a function that checks which machine we're on then
* does things correctly transparently or a function pointer which
* is setup at boot time to use the correct addresses.
* -- Cort
*/
/*
* Set the hardware clock. -- Cort
*/
__prep
int mc146818_set_rtc_time(unsigned long nowtime)
{
unsigned char save_control, save_freq_select;
struct rtc_time tm;
spin_lock(&rtc_lock);
to_tm(nowtime, &tm);
/* tell the clock it's being set */
save_control = CMOS_READ(RTC_CONTROL);
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
/* stop and reset prescaler */
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
tm.tm_year = (tm.tm_year - 1900) % 100;
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
BIN_TO_BCD(tm.tm_hour);
BIN_TO_BCD(tm.tm_mon);
BIN_TO_BCD(tm.tm_mday);
BIN_TO_BCD(tm.tm_year);
}
CMOS_WRITE(tm.tm_sec, RTC_SECONDS);
CMOS_WRITE(tm.tm_min, RTC_MINUTES);
CMOS_WRITE(tm.tm_hour, RTC_HOURS);
CMOS_WRITE(tm.tm_mon, RTC_MONTH);
CMOS_WRITE(tm.tm_mday, RTC_DAY_OF_MONTH);
CMOS_WRITE(tm.tm_year, RTC_YEAR);
/* The following flags have to be released exactly in this order,
* otherwise the DS12887 (popular MC146818A clone with integrated
* battery and quartz) will not reset the oscillator and will not
* update precisely 500 ms later. You won't find this mentioned in
* the Dallas Semiconductor data sheets, but who believes data
* sheets anyway ... -- Markus Kuhn
*/
CMOS_WRITE(save_control, RTC_CONTROL);
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
spin_unlock(&rtc_lock);
return 0;
}
__prep
unsigned long mc146818_get_rtc_time(void)
{
unsigned int year, mon, day, hour, min, sec;
int uip, i;
/* The Linux interpretation of the CMOS clock register contents:
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
* RTC registers show the second which has precisely just started.
* Let's hope other operating systems interpret the RTC the same way.
*/
/* Since the UIP flag is set for about 2.2 ms and the clock
* is typically written with a precision of 1 jiffy, trying
* to obtain a precision better than a few milliseconds is
* an illusion. Only consistency is interesting, this also
* allows to use the routine for /dev/rtc without a potential
* 1 second kernel busy loop triggered by any reader of /dev/rtc.
*/
for ( i = 0; i<1000000; i++) {
uip = CMOS_READ(RTC_FREQ_SELECT);
sec = CMOS_READ(RTC_SECONDS);
min = CMOS_READ(RTC_MINUTES);
hour = CMOS_READ(RTC_HOURS);
day = CMOS_READ(RTC_DAY_OF_MONTH);
mon = CMOS_READ(RTC_MONTH);
year = CMOS_READ(RTC_YEAR);
uip |= CMOS_READ(RTC_FREQ_SELECT);
if ((uip & RTC_UIP)==0) break;
}
if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
|| RTC_ALWAYS_BCD)
{
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hour);
BCD_TO_BIN(day);
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
}
if ((year += 1900) < 1970)
year += 100;
return mktime(year, mon, day, hour, min, sec);
}
__prep
int mk48t59_set_rtc_time(unsigned long nowtime)
{
unsigned char save_control;
struct rtc_time tm;
spin_lock(&rtc_lock);
to_tm(nowtime, &tm);
/* tell the clock it's being written */
save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA,
(save_control | MK48T59_RTC_CA_WRITE));
tm.tm_year = (tm.tm_year - 1900) % 100;
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
BIN_TO_BCD(tm.tm_hour);
BIN_TO_BCD(tm.tm_mon);
BIN_TO_BCD(tm.tm_mday);
BIN_TO_BCD(tm.tm_year);
ppc_md.nvram_write_val(MK48T59_RTC_SECONDS, tm.tm_sec);
ppc_md.nvram_write_val(MK48T59_RTC_MINUTES, tm.tm_min);
ppc_md.nvram_write_val(MK48T59_RTC_HOURS, tm.tm_hour);
ppc_md.nvram_write_val(MK48T59_RTC_MONTH, tm.tm_mon);
ppc_md.nvram_write_val(MK48T59_RTC_DAY_OF_MONTH, tm.tm_mday);
ppc_md.nvram_write_val(MK48T59_RTC_YEAR, tm.tm_year);
/* Turn off the write bit. */
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, save_control);
spin_unlock(&rtc_lock);
return 0;
}
__prep
unsigned long mk48t59_get_rtc_time(void)
{
unsigned char save_control;
unsigned int year, mon, day, hour, min, sec;
/* Simple: freeze the clock, read it and allow updates again */
save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
save_control &= ~MK48T59_RTC_CA_READ;
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, save_control);
/* Set the register to read the value. */
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA,
(save_control | MK48T59_RTC_CA_READ));
sec = ppc_md.nvram_read_val(MK48T59_RTC_SECONDS);
min = ppc_md.nvram_read_val(MK48T59_RTC_MINUTES);
hour = ppc_md.nvram_read_val(MK48T59_RTC_HOURS);
day = ppc_md.nvram_read_val(MK48T59_RTC_DAY_OF_MONTH);
mon = ppc_md.nvram_read_val(MK48T59_RTC_MONTH);
year = ppc_md.nvram_read_val(MK48T59_RTC_YEAR);
/* Let the time values change again. */
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, save_control);
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hour);
BCD_TO_BIN(day);
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
year = year + 1900;
if (year < 1970) {
year += 100;
}
return mktime(year, mon, day, hour, min, sec);
}
arch/ppc/platforms/spruce.h
View file @ f6eb8139
......@@ -35,11 +35,37 @@
#define SPRUCE_MEM_SIZE 0x04000000
#define SPRUCE_BUS_SPEED 66666667
#define SPRUCE_SERIAL_1_ADDR 0xff600300
#define SPRUCE_SERIAL_2_ADDR 0xff600400
#define SPRUCE_NVRAM_BASE_ADDR 0xff800000
#define SPRUCE_RTC_BASE_ADDR SPRUCE_NVRAM_BASE_ADDR
/*
* Serial port defines
*/
#define SPRUCE_FPGA_REG_A 0xff820000
#define SPRUCE_UARTCLK_33M 0x02
#define SPRUCE_UARTCLK_IS_33M(reg) (reg & SPRUCE_UARTCLK_33M)
#define UART0_IO_BASE 0xff600300
#define UART1_IO_BASE 0xff600400
#define RS_TABLE_SIZE 2
#define SPRUCE_BAUD_33M (33000000/64)
#define SPRUCE_BAUD_30M (30000000/64)
#define BASE_BAUD SPRUCE_BAUD_33M
#define UART0_INT 3
#define UART1_INT 4
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
ASYNC_BOOT_AUTOCONF, \
iomem_base: UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#define SERIAL_PORT_DFNS \
STD_UART_OP(0) \
STD_UART_OP(1)
#endif /* __ASM_SPRUCE_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/spruce_setup.c
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arch/ppc/syslib/Makefile
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......@@ -33,7 +33,7 @@ obj-$(CONFIG_PPC_OF) += prom_init.o prom.o of_device.o
obj-$(CONFIG_PPC_PMAC) += open_pic.o indirect_pci.o
obj-$(CONFIG_POWER4) += open_pic2.o
obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
......
arch/ppc/syslib/ppc4xx_setup.c
View file @ f6eb8139
......@@ -170,7 +170,7 @@ ppc4xx_calibrate_decr(void)
unsigned int freq;
bd_t *bip = &__res;
#if defined(CONFIG_WALNUT) || defined(CONFIG_CEDER)|| defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
/* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
#endif
......
arch/ppc64/Kconfig
View file @ f6eb8139
......@@ -87,6 +87,7 @@ config ALTIVEC
config PPC_PMAC
depends on PPC_PSERIES
bool "Apple PowerMac G5 support"
select ADB_PMU
config PPC_PMAC64
bool
......@@ -355,9 +356,16 @@ config MAGIC_SYSRQ
keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
unless you really know what this hack does.
config DEBUGGER
bool "Enable debugger hooks"
depends on DEBUG_KERNEL
help
Include in-kernel hooks for kernel debuggers. Unless you are
intending to debug the kernel, say N here.
config XMON
bool "Include xmon kernel debugger"
depends on DEBUG_KERNEL
depends on DEBUGGER
help
Include in-kernel hooks for the xmon kernel monitor/debugger.
Unless you are intending to debug the kernel, say N here.
......
arch/ppc64/boot/prom.c
View file @ f6eb8139
......@@ -11,9 +11,6 @@
#include <linux/string.h>
#include <linux/ctype.h>
#define BITS_PER_LONG 32
#include <asm/div64.h>
int (*prom)(void *);
void *chosen_handle;
......@@ -28,6 +25,9 @@ void chrpboot(int a1, int a2, void *prom); /* in main.c */
void printk(char *fmt, ...);
/* there is no convenient header to get this from... -- paulus */
extern unsigned long strlen(const char *);
int
write(void *handle, void *ptr, int nb)
{
......@@ -352,7 +352,7 @@ static int skip_atoi(const char **s)
#define SPECIAL 32 /* 0x */
#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */
static char * number(char * str, long long num, int base, int size, int precision, int type)
static char * number(char * str, long num, int base, int size, int precision, int type)
{
char c,sign,tmp[66];
const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
......@@ -388,8 +388,10 @@ static char * number(char * str, long long num, int base, int size, int precisio
i = 0;
if (num == 0)
tmp[i++]='0';
else while (num != 0)
tmp[i++] = digits[do_div(num,base)];
else while (num != 0) {
tmp[i++] = digits[num % base];
num /= base;
}
if (i > precision)
precision = i;
size -= precision;
......@@ -424,7 +426,7 @@ int sprintf(char * buf, const char *fmt, ...);
int vsprintf(char *buf, const char *fmt, va_list args)
{
int len;
unsigned long long num;
unsigned long num;
int i, base;
char * str;
const char *s;
......@@ -575,9 +577,7 @@ int vsprintf(char *buf, const char *fmt, va_list args)
--fmt;
continue;
}
if (qualifier == 'L')
num = va_arg(args, long long);
else if (qualifier == 'l') {
if (qualifier == 'l') {
num = va_arg(args, unsigned long);
if (flags & SIGN)
num = (signed long) num;
......
arch/ppc64/boot/zlib.c
View file @ f6eb8139
......@@ -102,9 +102,8 @@ extern char *z_errmsg[]; /* indexed by 1-zlib_error */
/* functions */
#include <linux/string.h>
extern void *memcpy(void *, const void *, unsigned long);
#define zmemcpy memcpy
#define zmemzero(dest, len) memset(dest, 0, len)
/* Diagnostic functions */
#ifdef DEBUG_ZLIB
......
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......@@ -6,5 +6,5 @@
# unless it's something special (ie not a .c file).
#
obj-y := mach.o
obj-y := mach.o setup.o
arch/sh/boards/hp6xx/hp680/mach.c
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