Commit f7061ffb authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski

ARM: dts: exynos: Fix mismatched value for SD4 pull up/down configuration on exynos4210

The pinctrl pull up/down register on exynos4210 is 2-bit wide for each
pin and it accepts only values of 0, 1 and 3.  The pins sd4-bus-width8
were configured with value of 4.  The driver does not validate the value
so this overflow effectively set a bit 1 in adjacent pins thus
configuring them to pull down.

The author's intention was probably to set drive strength of 4x.  All
other bus-widths pins are configured with pull up and drive strength of
4x.  Fix this one with same pattern.

Fixes: 87711d8c ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC")
Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent a2f2bc38
...@@ -649,7 +649,7 @@ sd4_bus4: sd4-bus-width4 { ...@@ -649,7 +649,7 @@ sd4_bus4: sd4-bus-width4 {
sd4_bus8: sd4-bus-width8 { sd4_bus8: sd4-bus-width8 {
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment