Commit f7f7a8f4 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Linus Walleij

ARM: dts: arm-realview: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
    l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200626080534.3400-1-krzk@kernel.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent b3a9e3b9
......@@ -59,7 +59,7 @@ intc_second: interrupt-controller@10040000 {
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc>;
......
......@@ -323,7 +323,7 @@ intc_dc1176: interrupt-controller@10120000 {
<0x10120000 0x100>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x10110000 0x1000>;
interrupt-parent = <&intc_dc1176>;
......
......@@ -92,7 +92,7 @@ intc_tc11mp: interrupt-controller@1f000100 {
<0x1f000100 0x100>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
......
......@@ -60,7 +60,7 @@ CPU1: cpu@1 {
};
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x1f002000 0x1000>;
cache-unified;
......
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