Commit f7ff3cff authored by Alex Bee's avatar Alex Bee Committed by Joerg Roedel

iommu/rockchip: Fix PAGE_DESC_HI_MASKs for RK3568

With the submission of iommu driver for RK3568 a subtle bug was
introduced: PAGE_DESC_HI_MASK1 and PAGE_DESC_HI_MASK2 have to be
the other way arround - that leads to random errors, especially when
addresses beyond 32 bit are used.

Fix it.

Fixes: c55356c5 ("iommu: rockchip: Add support for iommu v2")
Signed-off-by: default avatarAlex Bee <knaerzche@gmail.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: default avatarDan Johansen <strit@manjaro.org>
Reviewed-by: default avatarBenjamin Gaignard <benjamin.gaignard@collabora.com>
Link: https://lore.kernel.org/r/20211124021325.858139-1-knaerzche@gmail.comSigned-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 717e88aa
...@@ -200,8 +200,8 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte) ...@@ -200,8 +200,8 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
#define DTE_HI_MASK2 GENMASK(7, 4) #define DTE_HI_MASK2 GENMASK(7, 4)
#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36) #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)
#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32) #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)
static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
{ {
......
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