Commit f8b13d9b authored by Maxime Ripard's avatar Maxime Ripard

drm/vc4: hvs: Make sure our channel is reset

In order to clear our intermediate FIFOs that might end up with a stale
pixel, let's make sure our FIFO channel is reset every time our channel is
setup.
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Tested-by: default avatarHoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b34c562b36177c758dd2e9d84bceb07689bfbe05.1599120059.git-series.maxime@cerno.tech
parent d2f06525
...@@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, ...@@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
u32 dispbkgndx; u32 dispbkgndx;
u32 dispctrl; u32 dispctrl;
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
/* Turn on the scaler, which will wait for vstart to start /* Turn on the scaler, which will wait for vstart to start
* compositing. * compositing.
* When feeding the transposer, we should operate in oneshot * When feeding the transposer, we should operate in oneshot
......
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