Commit f97c81dc authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC late updates from Arnd Bergmann:
 "This is some material that we picked up into our tree late or that had
  complex inter-depondencies. The fact that there are these
  interdependencies tends to meant that these are often actually the
  most interesting new additions:

   - The new Aspeed AST2600 baseboard management controller is added,
     this is a Cortex-A7 based follow-up to the ARM11 based AST2500 and
     had some dependencies on other device drivers.

   - After many years, support for the MMP2 based OLPC XO-1.75 finally
     makes it into the kernel.

   - The Armada 3720 based Turris Mox open source router platform is a
     late addition and it follows some preparatory work across multiple
     branches.

   - The OMAP2+ platform had some large-scale cleanup involving driver
     changes and DT changes, here we finish it off, dropping a lot of
     the now-unused platform data.

   - The TI K3 platform that got added for 5.3 gains a lot more support
     for individual bits on the SoC, this part just came late for the
     merge window"

[ This pull request itself wasn't actually sent late at all by Arnd, but
  I waited on the branches that it used to be pulled first, so it ends
  up being merged much later than the other ARM SoC pull requests this
  merge window     - Linus ]

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
  ARM: dts: dir685: Drop spi-cpol from the display
  ARM: dts: aspeed: Add AST2600 pinmux nodes
  ARM: dts: aspeed: Add AST2600 and EVB
  ARM: exynos: Enable support for ARM architected timers
  ARM: samsung: Fix system restart on S3C6410
  ARM: dts: mmp2: add OLPC XO 1.75 machine
  ARM: dts: mmp2: rename the USB PHY node
  ARM: dts: mmp2: specify reg-shift for the UARTs
  ARM: dts: mmp2: add camera interfaces
  ARM: dts: mmp2: fix the SPI nodes
  ARM: dts: mmp2: trivial whitespace fix
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-j721e-main: Add hwspinlock node
  arm64: dts: ti: k3-am65-main: Add hwspinlock node
  arm64: dts: k3-j721e: Add gpio-keys on common processor board
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
  ...
parents a703d279 2a7326ca
...@@ -48,3 +48,11 @@ avs: avs@11500 { ...@@ -48,3 +48,11 @@ avs: avs@11500 {
compatible = "marvell,armada-3700-avs", "syscon"; compatible = "marvell,armada-3700-avs", "syscon";
reg = <0x11500 0x40>; reg = <0x11500 0x40>;
} }
CZ.NIC's Turris Mox SOHO router Device Tree Bindings
----------------------------------------------------
Required root node property:
- compatible: must contain "cznic,turris-mox"
...@@ -11867,6 +11867,7 @@ S: Maintained ...@@ -11867,6 +11867,7 @@ S: Maintained
F: arch/arm/mach-omap2/ F: arch/arm/mach-omap2/
F: arch/arm/plat-omap/ F: arch/arm/plat-omap/
F: arch/arm/configs/omap2plus_defconfig F: arch/arm/configs/omap2plus_defconfig
F: drivers/bus/ti-sysc.c
F: drivers/i2c/busses/i2c-omap.c F: drivers/i2c/busses/i2c-omap.c
F: drivers/irqchip/irq-omap-intc.c F: drivers/irqchip/irq-omap-intc.c
F: drivers/mfd/*omap*.c F: drivers/mfd/*omap*.c
...@@ -11887,6 +11888,7 @@ F: drivers/regulator/tps65910-regulator.c ...@@ -11887,6 +11888,7 @@ F: drivers/regulator/tps65910-regulator.c
F: drivers/regulator/twl-regulator.c F: drivers/regulator/twl-regulator.c
F: drivers/regulator/twl6030-regulator.c F: drivers/regulator/twl6030-regulator.c
F: include/linux/platform_data/i2c-omap.h F: include/linux/platform_data/i2c-omap.h
F: include/linux/platform_data/ti-sysc.h
ONION OMEGA2+ BOARD ONION OMEGA2+ BOARD
M: Harvey Hunt <harveyhuntnexus@gmail.com> M: Harvey Hunt <harveyhuntnexus@gmail.com>
......
...@@ -336,7 +336,8 @@ dtb-$(CONFIG_MACH_MESON8) += \ ...@@ -336,7 +336,8 @@ dtb-$(CONFIG_MACH_MESON8) += \
dtb-$(CONFIG_ARCH_MMP) += \ dtb-$(CONFIG_ARCH_MMP) += \
pxa168-aspenite.dtb \ pxa168-aspenite.dtb \
pxa910-dkb.dtb \ pxa910-dkb.dtb \
mmp2-brownstone.dtb mmp2-brownstone.dtb \
mmp2-olpc-xo-1-75.dtb
dtb-$(CONFIG_ARCH_MPS2) += \ dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an385.dtb \ mps2-an385.dtb \
mps2-an399.dtb mps2-an399.dtb
...@@ -1278,6 +1279,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb ...@@ -1278,6 +1279,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \ aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-cmm.dtb \
......
...@@ -673,7 +673,6 @@ segment@0 { /* 0x4a000000 */ ...@@ -673,7 +673,6 @@ segment@0 { /* 0x4a000000 */
target-module@100000 { /* 0x4a100000, ap 3 08.0 */ target-module@100000 { /* 0x4a100000, ap 3 08.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc"; compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "cpgmac0";
reg = <0x101200 0x4>, reg = <0x101200 0x4>,
<0x101208 0x4>, <0x101208 0x4>,
<0x101204 0x4>; <0x101204 0x4>;
...@@ -719,9 +718,10 @@ mac: ethernet@0 { ...@@ -719,9 +718,10 @@ mac: ethernet@0 {
davinci_mdio: mdio@1000 { davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio"; compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>; bus_freq = <1000000>;
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
status = "disabled"; status = "disabled";
......
...@@ -88,6 +88,30 @@ hecc: can@5c050000 { ...@@ -88,6 +88,30 @@ hecc: can@5c050000 {
interrupts = <24>; interrupts = <24>;
clocks = <&hecc_ck>; clocks = <&hecc_ck>;
}; };
/*
* On am3517 the OCP registers do not seem to be accessible
* similar to the omap34xx. Maybe SGX is permanently set to
* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
* write-only at 0x50000e10. We detect SGX based on the SGX
* revision register instead of the unreadable OCP revision
* register.
*/
sgx_module: target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000014 0x4>;
reg-names = "rev";
clocks = <&sgx_fck>, <&sgx_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x4000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
}; };
}; };
......
...@@ -512,7 +512,6 @@ segment@0 { /* 0x4a000000 */ ...@@ -512,7 +512,6 @@ segment@0 { /* 0x4a000000 */
target-module@100000 { /* 0x4a100000, ap 3 04.0 */ target-module@100000 { /* 0x4a100000, ap 3 04.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc"; compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "cpgmac0";
reg = <0x101200 0x4>, reg = <0x101200 0x4>,
<0x101208 0x4>, <0x101208 0x4>,
<0x101204 0x4>; <0x101204 0x4>;
...@@ -559,11 +558,10 @@ GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH ...@@ -559,11 +558,10 @@ GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
davinci_mdio: mdio@1000 { davinci_mdio: mdio@1000 {
compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>; bus_freq = <1000000>;
status = "disabled"; status = "disabled";
}; };
......
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2019 IBM Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
/ {
model = "AST2600 EVB";
compatible = "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
bootargs = "console=ttyS4,115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
};
&mdio1 {
status = "okay";
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mdio2 {
status = "okay";
ethphy2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mdio3 {
status = "okay";
ethphy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mac1 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
};
&mac2 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
};
&mac3 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy3>;
};
&emmc {
status = "okay";
};
&rtc {
status = "okay";
};
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// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2019 IBM Corp.
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/ast2600-clock.h>
/ {
model = "Aspeed BMC";
compatible = "aspeed,ast2600";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
serial4 = &uart5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "aspeed,ast2600-smp";
cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
};
cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
clocks = <&syscon ASPEED_CLK_HPLL>;
arm,cpu-registers-not-fw-configured;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges;
gic: interrupt-controller@40461000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
reg = <0x40461000 0x1000>,
<0x40462000 0x1000>,
<0x40464000 0x2000>,
<0x40466000 0x2000>;
};
mdio0: mdio@1e650000 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650000 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mdio1: mdio@1e650008 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650008 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mdio2: mdio@1e650010 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650010 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mdio3: mdio@1e650018 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650018 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mac0: ftgmac@1e660000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
mac1: ftgmac@1e680000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
mac2: ftgmac@1e670000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e670000 0x180>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
status = "disabled";
};
mac3: ftgmac@1e690000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e690000 0x180>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
status = "disabled";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1000>;
ranges = <0 0x1e6e2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2600-pinctrl";
};
smp-memram@180 {
compatible = "aspeed,ast2600-smpmem";
reg = <0x180 0x40>;
};
};
rng: hwrng@1e6e2524 {
compatible = "timeriomem_rng";
reg = <0x1e6e2524 0x4>;
period = <1>;
quality = <100>;
};
rtc: rtc@1e781000 {
compatible = "aspeed,ast2600-rtc";
reg = <0x1e781000 0x18>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart5: serial@1e784000 {
compatible = "ns16550a";
reg = <0x1e784000 0x1000>;
reg-shift = <2>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
};
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
};
sdc: sdc@1e740000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x100 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x200 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
};
emmc: sdc@1e750000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e750000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e750000 0x10000>;
clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
status = "disabled";
sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
sdhci,auto-cmd12;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_EMMC>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_default>;
};
};
};
};
};
#include "aspeed-g6-pinctrl.dtsi"
This diff is collapsed.
...@@ -72,7 +72,6 @@ panel: display@0 { ...@@ -72,7 +72,6 @@ panel: display@0 {
reg = <0>; reg = <0>;
/* 50 ns min period = 20 MHz */ /* 50 ns min period = 20 MHz */
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
spi-cpol; /* Clock active low */
vcc-supply = <&vdisp>; vcc-supply = <&vdisp>;
iovcc-supply = <&vdisp>; iovcc-supply = <&vdisp>;
vci-supply = <&vdisp>; vci-supply = <&vdisp>;
......
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* OLPC XO 1.75 Laptop.
*
* Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
*/
/dts-v1/;
#include "mmp2.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "OLPC XO-1.75";
compatible = "olpc,xo-1.75", "mrvl,mmp2";
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
framebuffer@1fc00000 {
compatible = "simple-framebuffer";
reg = <0x1fc00000 (1200 * 900 * 2)>;
width = <1200>;
height = <900>;
stride = <(1200 * 2)>;
format = "r5g6b5";
clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>,
<&soc_clocks MMP2_CLK_DISP0>;
};
};
memory {
linux,usable-memory = <0x0 0x1f800000>;
available = <0xcf000 0x1ef31000 0x1000 0xbf000>;
reg = <0x0 0x20000000>;
device_type = "memory";
};
gpio-keys {
compatible = "gpio-keys";
lid {
label = "Lid";
gpios = <&gpio 129 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
};
tablet_mode {
label = "E-Book Mode";
gpios = <&gpio 128 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_TABLET_MODE>;
wakeup-source;
};
microphone_insert {
label = "Microphone Plug";
gpios = <&gpio 96 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_SW>;
linux,code = <SW_MICROPHONE_INSERT>;
debounce-interval = <100>;
wakeup-source;
};
headphone_insert {
label = "Headphone Plug";
gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_SW>;
linux,code = <SW_HEADPHONE_INSERT>;
debounce-interval = <100>;
wakeup-source;
};
};
camera_i2c {
compatible = "i2c-gpio";
gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
<&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
i2c-gpio,timeout-ms = <1000>;
status = "okay";
camera@21 {
compatible = "ovti,ov7670";
reg = <0x21>;
reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>;
clocks = <&camera0>;
clock-names = "xclk";
port {
ov7670_0: endpoint {
hsync-active = <1>;
vsync-active = <1>;
remote-endpoint = <&camera0_0>;
};
};
};
};
battery {
compatible = "olpc,xo1.5-battery", "olpc,xo1-battery";
};
wlan_reg: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "wlan";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio 34 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
wlan_pwrseq: pwrseq0 {
compatible = "mmc-pwrseq-sd8787";
powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
};
soc {
axi@d4200000 {
ap-sp@d4290000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "olpc,ap-sp";
interrupts = <40>;
reg = <0xd4290000 0x1000>;
data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
};
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&rtc {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb_otg0 {
status = "okay";
};
&mmc1 {
clock-frequency = <50000000>;
no-1-8-v;
mrvl,clk-delay-cycles = <31>;
broken-cd;
status = "okay";
};
&mmc2 {
clock-frequency = <50000000>;
no-1-8-v;
bus-width = <4>;
non-removable;
broken-cd;
wakeup-source;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
vmmc-supply = <&wlan_reg>;
status = "okay";
};
&mmc3 {
clock-frequency = <50000000>;
no-1-8-v;
bus-width = <8>;
non-removable;
broken-cd;
mrvl,clk-delay-cycles = <31>;
status = "okay";
};
&twsi1 {
status = "okay";
audio-codec@1a {
compatible = "realtek,alc5631";
reg = <0x1a>;
status = "okay";
};
};
&twsi2 {
status = "okay";
rtc@68 {
compatible = "dallas,ds1338";
reg = <0x68>;
status = "okay";
};
};
&twsi6 {
status = "okay";
accelerometer@1d {
compatible = "st,lis331dlh", "st,lis3lv02d";
reg = <0x1d>;
status = "okay";
};
};
&ssp3 {
#address-cells = <0>;
spi-slave;
status = "okay";
ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
&camera0 {
status = "okay";
port {
camera0_0: endpoint {
remote-endpoint = <&ov7670_0>;
};
};
};
...@@ -117,7 +117,7 @@ intcmux55: interrupt-controller@d4282188 { ...@@ -117,7 +117,7 @@ intcmux55: interrupt-controller@d4282188 {
mrvl,intc-nr-irqs = <2>; mrvl,intc-nr-irqs = <2>;
}; };
usb_otg_phy0: usb-otg-phy@d4207000 { usb_phy0: usb-phy@d4207000 {
compatible = "marvell,mmp2-usb-phy"; compatible = "marvell,mmp2-usb-phy";
reg = <0xd4207000 0x40>; reg = <0xd4207000 0x40>;
#phy-cells = <0>; #phy-cells = <0>;
...@@ -130,7 +130,7 @@ usb_otg0: usb-otg@d4208000 { ...@@ -130,7 +130,7 @@ usb_otg0: usb-otg@d4208000 {
interrupts = <44>; interrupts = <44>;
clocks = <&soc_clocks MMP2_CLK_USB>; clocks = <&soc_clocks MMP2_CLK_USB>;
clock-names = "USBCLK"; clock-names = "USBCLK";
phys = <&usb_otg_phy0>; phys = <&usb_phy0>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
}; };
...@@ -170,6 +170,28 @@ mmc4: mmc@d4281800 { ...@@ -170,6 +170,28 @@ mmc4: mmc@d4281800 {
interrupts = <54>; interrupts = <54>;
status = "disabled"; status = "disabled";
}; };
camera0: camera@d420a000 {
compatible = "marvell,mmp2-ccic";
reg = <0xd420a000 0x800>;
interrupts = <42>;
clocks = <&soc_clocks MMP2_CLK_CCIC0>;
clock-names = "axi";
#clock-cells = <0>;
clock-output-names = "mclk";
status = "disabled";
};
camera1: camera@d420a800 {
compatible = "marvell,mmp2-ccic";
reg = <0xd420a800 0x800>;
interrupts = <30>;
clocks = <&soc_clocks MMP2_CLK_CCIC1>;
clock-names = "axi";
#clock-cells = <0>;
clock-output-names = "mclk";
status = "disabled";
};
}; };
apb@d4000000 { /* APB */ apb@d4000000 { /* APB */
...@@ -192,6 +214,7 @@ uart1: uart@d4030000 { ...@@ -192,6 +214,7 @@ uart1: uart@d4030000 {
interrupts = <27>; interrupts = <27>;
clocks = <&soc_clocks MMP2_CLK_UART0>; clocks = <&soc_clocks MMP2_CLK_UART0>;
resets = <&soc_clocks MMP2_CLK_UART0>; resets = <&soc_clocks MMP2_CLK_UART0>;
reg-shift = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -201,6 +224,7 @@ uart2: uart@d4017000 { ...@@ -201,6 +224,7 @@ uart2: uart@d4017000 {
interrupts = <28>; interrupts = <28>;
clocks = <&soc_clocks MMP2_CLK_UART1>; clocks = <&soc_clocks MMP2_CLK_UART1>;
resets = <&soc_clocks MMP2_CLK_UART1>; resets = <&soc_clocks MMP2_CLK_UART1>;
reg-shift = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -210,6 +234,7 @@ uart3: uart@d4018000 { ...@@ -210,6 +234,7 @@ uart3: uart@d4018000 {
interrupts = <24>; interrupts = <24>;
clocks = <&soc_clocks MMP2_CLK_UART2>; clocks = <&soc_clocks MMP2_CLK_UART2>;
resets = <&soc_clocks MMP2_CLK_UART2>; resets = <&soc_clocks MMP2_CLK_UART2>;
reg-shift = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -219,6 +244,7 @@ uart4: uart@d4016000 { ...@@ -219,6 +244,7 @@ uart4: uart@d4016000 {
interrupts = <46>; interrupts = <46>;
clocks = <&soc_clocks MMP2_CLK_UART3>; clocks = <&soc_clocks MMP2_CLK_UART3>;
resets = <&soc_clocks MMP2_CLK_UART3>; resets = <&soc_clocks MMP2_CLK_UART3>;
reg-shift = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -346,40 +372,48 @@ rtc: rtc@d4010000 { ...@@ -346,40 +372,48 @@ rtc: rtc@d4010000 {
status = "disabled"; status = "disabled";
}; };
ssp1: ssp@d4035000 { ssp1: spi@d4035000 {
compatible = "marvell,mmp2-ssp"; compatible = "marvell,mmp2-ssp";
reg = <0xd4035000 0x1000>; reg = <0xd4035000 0x1000>;
clocks = <&soc_clocks MMP2_CLK_SSP0>; clocks = <&soc_clocks MMP2_CLK_SSP0>;
interrupts = <0>; interrupts = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ssp2: ssp@d4036000 { ssp2: spi@d4036000 {
compatible = "marvell,mmp2-ssp"; compatible = "marvell,mmp2-ssp";
reg = <0xd4036000 0x1000>; reg = <0xd4036000 0x1000>;
clocks = <&soc_clocks MMP2_CLK_SSP1>; clocks = <&soc_clocks MMP2_CLK_SSP1>;
interrupts = <1>; interrupts = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ssp3: ssp@d4037000 { ssp3: spi@d4037000 {
compatible = "marvell,mmp2-ssp"; compatible = "marvell,mmp2-ssp";
reg = <0xd4037000 0x1000>; reg = <0xd4037000 0x1000>;
clocks = <&soc_clocks MMP2_CLK_SSP2>; clocks = <&soc_clocks MMP2_CLK_SSP2>;
interrupts = <20>; interrupts = <20>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ssp4: ssp@d4039000 { ssp4: spi@d4039000 {
compatible = "marvell,mmp2-ssp"; compatible = "marvell,mmp2-ssp";
reg = <0xd4039000 0x1000>; reg = <0xd4039000 0x1000>;
clocks = <&soc_clocks MMP2_CLK_SSP3>; clocks = <&soc_clocks MMP2_CLK_SSP3>;
interrupts = <21>; interrupts = <21>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
}; };
soc_clocks: clocks{ soc_clocks: clocks {
compatible = "marvell,mmp2-clock"; compatible = "marvell,mmp2-clock";
reg = <0xd4050000 0x1000>, reg = <0xd4050000 0x1000>,
<0xd4282800 0x400>, <0xd4282800 0x400>,
......
...@@ -100,6 +100,32 @@ smartreflex_mpu_iva: smartreflex@480c9000 { ...@@ -100,6 +100,32 @@ smartreflex_mpu_iva: smartreflex@480c9000 {
interrupts = <18>; interrupts = <18>;
}; };
}; };
/*
* On omap34xx the OCP registers do not seem to be accessible
* at all unlike on 36xx. Maybe SGX is permanently set to
* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
* write-only at 0x50000e10. We detect SGX based on the SGX
* revision register instead of the unreadable OCP revision
* register. Also note that on early 34xx es1 revision there
* are also different clocks, but we do not have any dts users
* for it.
*/
sgx_module: target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000014 0x4>;
reg-names = "rev";
clocks = <&sgx_fck>, <&sgx_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x4000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
}; };
thermal_zones: thermal-zones { thermal_zones: thermal-zones {
......
...@@ -139,6 +139,34 @@ smartreflex_mpu_iva: smartreflex@480c9000 { ...@@ -139,6 +139,34 @@ smartreflex_mpu_iva: smartreflex@480c9000 {
interrupts = <18>; interrupts = <18>;
}; };
}; };
/*
* Note that the sysconfig register layout is a subset of the
* "ti,sysc-omap4" type register with just sidle and midle bits
* available while omap34xx has "ti,sysc-omap2" type sysconfig.
*/
sgx_module: target-module@50000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5000fe00 0x4>,
<0x5000fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&sgx_fck>, <&sgx_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x2000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
}; };
thermal_zones: thermal-zones { thermal_zones: thermal-zones {
......
...@@ -255,7 +255,6 @@ dmic: dmic@0 { ...@@ -255,7 +255,6 @@ dmic: dmic@0 {
target-module@30000 { /* 0x40130000, ap 14 0e.0 */ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer3";
reg = <0x30000 0x4>, reg = <0x30000 0x4>,
<0x30010 0x4>, <0x30010 0x4>,
<0x30014 0x4>; <0x30014 0x4>;
......
...@@ -456,17 +456,43 @@ usb2_phy: usb2phy@80 { ...@@ -456,17 +456,43 @@ usb2_phy: usb2phy@80 {
}; };
}; };
/* d2d mdm */
target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
compatible = "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
status = "disabled"; reg = <0x36000 0x4>,
<0x36010 0x4>,
<0x36014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x36000 0x1000>; ranges = <0x0 0x36000 0x1000>;
}; };
/* d2d mpu */
target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
compatible = "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
status = "disabled"; reg = <0x4d000 0x4>,
<0x4d010 0x4>,
<0x4d014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x4d000 0x1000>; ranges = <0x0 0x4d000 0x1000>;
...@@ -1094,7 +1120,6 @@ gpio1: gpio@0 { ...@@ -1094,7 +1120,6 @@ gpio1: gpio@0 {
target-module@4000 { /* 0x4a314000, ap 7 18.0 */ target-module@4000 { /* 0x4a314000, ap 7 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>, reg = <0x4000 0x4>,
<0x4010 0x4>, <0x4010 0x4>,
<0x4014 0x4>; <0x4014 0x4>;
...@@ -1695,7 +1720,6 @@ gpio6: gpio@0 { ...@@ -1695,7 +1720,6 @@ gpio6: gpio@0 {
target-module@60000 { /* 0x48060000, ap 25 1e.0 */ target-module@60000 { /* 0x48060000, ap 25 1e.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x60000 0x8>, reg = <0x60000 0x8>,
<0x60010 0x8>, <0x60010 0x8>,
<0x60090 0x8>; <0x60090 0x8>;
...@@ -1814,7 +1838,6 @@ uart4: serial@0 { ...@@ -1814,7 +1838,6 @@ uart4: serial@0 {
target-module@70000 { /* 0x48070000, ap 32 28.0 */ target-module@70000 { /* 0x48070000, ap 32 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0x70000 0x8>, reg = <0x70000 0x8>,
<0x70010 0x8>, <0x70010 0x8>,
<0x70090 0x8>; <0x70090 0x8>;
...@@ -1846,7 +1869,6 @@ i2c1: i2c@0 { ...@@ -1846,7 +1869,6 @@ i2c1: i2c@0 {
target-module@72000 { /* 0x48072000, ap 34 30.0 */ target-module@72000 { /* 0x48072000, ap 34 30.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x72000 0x8>, reg = <0x72000 0x8>,
<0x72010 0x8>, <0x72010 0x8>,
<0x72090 0x8>; <0x72090 0x8>;
...@@ -2401,7 +2423,6 @@ segment@200000 { /* 0x48200000 */ ...@@ -2401,7 +2423,6 @@ segment@200000 { /* 0x48200000 */
target-module@150000 { /* 0x48350000, ap 77 4c.0 */ target-module@150000 { /* 0x48350000, ap 77 4c.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c4";
reg = <0x150000 0x8>, reg = <0x150000 0x8>,
<0x150010 0x8>, <0x150010 0x8>,
<0x150090 0x8>; <0x150090 0x8>;
......
...@@ -330,7 +330,6 @@ abb_iva: regulator-abb-iva { ...@@ -330,7 +330,6 @@ abb_iva: regulator-abb-iva {
target-module@56000000 { target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc"; compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "gpu";
reg = <0x5601fc00 0x4>, reg = <0x5601fc00 0x4>,
<0x5601fc10 0x4>; <0x5601fc10 0x4>;
reg-names = "rev", "sysc"; reg-names = "rev", "sysc";
......
...@@ -257,6 +257,29 @@ sata: sata@4a141100 { ...@@ -257,6 +257,29 @@ sata: sata@4a141100 {
ports-implemented = <0x1>; ports-implemented = <0x1>;
}; };
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
dss: dss@58000000 { dss: dss@58000000 {
compatible = "ti,omap5-dss"; compatible = "ti,omap5-dss";
reg = <0x58000000 0x80>; reg = <0x58000000 0x80>;
......
...@@ -1146,6 +1146,20 @@ dss_clkctrl: clk@20 { ...@@ -1146,6 +1146,20 @@ dss_clkctrl: clk@20 {
}; };
}; };
gpu_cm: clock-controller@1500 {
compatible = "ti,omap4-cm";
reg = <0x1500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1500 0x100>;
gpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l3init_cm: l3init_cm@1600 { l3init_cm: l3init_cm@1600 {
compatible = "ti,omap4-cm"; compatible = "ti,omap4-cm";
reg = <0x1600 0x100>; reg = <0x1600 0x100>;
......
...@@ -19,6 +19,7 @@ menuconfig ARCH_EXYNOS ...@@ -19,6 +19,7 @@ menuconfig ARCH_EXYNOS
select EXYNOS_SROM select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select GPIOLIB select GPIOLIB
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 && VIRTUALIZATION
select HAVE_ARM_SCU if SMP select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
......
...@@ -30,7 +30,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; ...@@ -30,7 +30,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0; extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1; extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
...@@ -72,8 +71,6 @@ extern struct omap_hwmod am33xx_rng_hwmod; ...@@ -72,8 +71,6 @@ extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_cpgmac0_hwmod;
extern struct omap_hwmod am33xx_mdio_hwmod;
extern struct omap_hwmod am33xx_dcan0_hwmod; extern struct omap_hwmod am33xx_dcan0_hwmod;
extern struct omap_hwmod am33xx_dcan1_hwmod; extern struct omap_hwmod am33xx_dcan1_hwmod;
extern struct omap_hwmod am33xx_elm_hwmod; extern struct omap_hwmod am33xx_elm_hwmod;
......
...@@ -122,12 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { ...@@ -122,12 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod,
.user = OCP_USER_MPU,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod, .slave = &am33xx_elm_hwmod,
......
...@@ -349,54 +349,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = { ...@@ -349,54 +349,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control", .name = "control",
}; };
/*
* 'cpgmac' class
* cpsw/cpgmac sub system
*/
static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.name = "cpgmac0",
.sysc = &am33xx_cpgmac_sysc,
};
struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "cpsw_125mhz_gclk",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* mdio class
*/
static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
.name = "davinci_mdio",
};
struct omap_hwmod am33xx_mdio_hwmod = {
.name = "davinci_mdio",
.class = &am33xx_mdio_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.main_clk = "cpsw_125mhz_gclk",
};
/* /*
* dcan class * dcan class
*/ */
...@@ -1072,7 +1024,6 @@ static void omap_hwmod_am33xx_clkctrl(void) ...@@ -1072,7 +1024,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET); CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET); CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET); CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
...@@ -1134,7 +1085,6 @@ static void omap_hwmod_am43xx_clkctrl(void) ...@@ -1134,7 +1085,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET); CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET); CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET); CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
......
...@@ -372,13 +372,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { ...@@ -372,13 +372,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
.master = &am33xx_l3_main_hwmod, .master = &am33xx_l3_main_hwmod,
.slave = &am33xx_lcdc_hwmod, .slave = &am33xx_lcdc_hwmod,
...@@ -462,8 +455,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { ...@@ -462,8 +455,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc2, &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc, &am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss, &am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0, &am33xx_l3_main__sha0,
&am33xx_l3_main__aes0, &am33xx_l3_main__aes0,
&am33xx_l4_per__rng, &am33xx_l4_per__rng,
......
...@@ -597,13 +597,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = { ...@@ -597,13 +597,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
.master = &am43xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod, .master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod, .slave = &am33xx_timer1_hwmod,
...@@ -859,8 +852,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { ...@@ -859,8 +852,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc1, &am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2, &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc, &am33xx_l3_main__ocmc,
&am43xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0, &am33xx_l3_main__sha0,
&am33xx_l3_main__aes0, &am33xx_l3_main__aes0,
&am43xx_l3_main__des, &am43xx_l3_main__des,
......
...@@ -28,7 +28,6 @@ ...@@ -28,7 +28,6 @@
#include "cm2_44xx.h" #include "cm2_44xx.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "prm-regbits-44xx.h" #include "prm-regbits-44xx.h"
#include "wd_timer.h"
/* Base offset for all OMAP4 interrupts external to MPUSS */ /* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START 32 #define OMAP44XX_IRQ_GIC_START 32
...@@ -275,29 +274,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = { ...@@ -275,29 +274,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
}, },
}; };
/*
* 'c2c' class
* chip 2 chip interface used to plug the ape soc (omap) with an external modem
* soc
*/
static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
.name = "c2c",
};
/* c2c */
static struct omap_hwmod omap44xx_c2c_hwmod = {
.name = "c2c",
.class = &omap44xx_c2c_hwmod_class,
.clkdm_name = "d2d_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
},
},
};
/* /*
* 'counter' class * 'counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
...@@ -1085,41 +1061,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { ...@@ -1085,41 +1061,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
}, },
}; };
/*
* 'gpu' class
* 2d/3d graphics accelerator
*/
static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
.rev_offs = 0x1fc00,
.sysc_offs = 0x1fc10,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
.name = "gpu",
.sysc = &omap44xx_gpu_sysc,
};
/* gpu */
static struct omap_hwmod omap44xx_gpu_hwmod = {
.name = "gpu",
.class = &omap44xx_gpu_hwmod_class,
.clkdm_name = "l3_gfx_clkdm",
.main_clk = "sgx_clk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* /*
* 'hdq1w' class * 'hdq1w' class
* hdq / 1-wire serial interface controller * hdq / 1-wire serial interface controller
...@@ -2433,61 +2374,6 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { ...@@ -2433,61 +2374,6 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
}, },
}; };
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap44xx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
.reset = &omap2_wd_timer_reset,
};
/* wd_timer2 */
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* wd_timer3 */
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* /*
* interfaces * interfaces
*/ */
...@@ -2596,14 +2482,6 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { ...@@ -2596,14 +2482,6 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* gpu -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
.master = &omap44xx_gpu_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* hsi -> l3_main_2 */ /* hsi -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
.master = &omap44xx_hsi_hwmod, .master = &omap44xx_hsi_hwmod,
...@@ -2788,14 +2666,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { ...@@ -2788,14 +2666,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
.user = OCP_USER_SDMA, .user = OCP_USER_SDMA,
}; };
/* l3_main_2 -> c2c */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_c2c_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */ /* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.master = &omap44xx_l4_wkup_hwmod, .master = &omap44xx_l4_wkup_hwmod,
...@@ -3028,14 +2898,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { ...@@ -3028,14 +2898,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l3_main_2 -> gpu */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_gpu_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> hdq1w */ /* l4_per -> hdq1w */
static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
.master = &omap44xx_l4_per_hwmod, .master = &omap44xx_l4_per_hwmod,
...@@ -3396,30 +3258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { ...@@ -3396,30 +3258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> wd_timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> wd_timer3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_SDMA,
};
/* mpu -> emif1 */ /* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
.master = &omap44xx_mpu_hwmod, .master = &omap44xx_mpu_hwmod,
...@@ -3450,7 +3288,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3450,7 +3288,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_debugss__l3_main_2, &omap44xx_debugss__l3_main_2,
&omap44xx_dma_system__l3_main_2, &omap44xx_dma_system__l3_main_2,
&omap44xx_fdif__l3_main_2, &omap44xx_fdif__l3_main_2,
&omap44xx_gpu__l3_main_2,
&omap44xx_hsi__l3_main_2, &omap44xx_hsi__l3_main_2,
&omap44xx_ipu__l3_main_2, &omap44xx_ipu__l3_main_2,
&omap44xx_iss__l3_main_2, &omap44xx_iss__l3_main_2,
...@@ -3474,7 +3311,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3474,7 +3311,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__ocp_wp_noc, &omap44xx_l4_cfg__ocp_wp_noc,
&omap44xx_l4_abe__aess, &omap44xx_l4_abe__aess,
&omap44xx_l4_abe__aess_dma, &omap44xx_l4_abe__aess_dma,
&omap44xx_l3_main_2__c2c,
&omap44xx_l4_wkup__counter_32k, &omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core, &omap44xx_l4_cfg__ctrl_module_core,
&omap44xx_l4_cfg__ctrl_module_pad_core, &omap44xx_l4_cfg__ctrl_module_pad_core,
...@@ -3503,7 +3339,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3503,7 +3339,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_per__elm, &omap44xx_l4_per__elm,
&omap44xx_l4_cfg__fdif, &omap44xx_l4_cfg__fdif,
&omap44xx_l3_main_2__gpmc, &omap44xx_l3_main_2__gpmc,
&omap44xx_l3_main_2__gpu,
&omap44xx_l4_per__hdq1w, &omap44xx_l4_per__hdq1w,
&omap44xx_l4_cfg__hsi, &omap44xx_l4_cfg__hsi,
&omap44xx_l3_main_2__ipu, &omap44xx_l3_main_2__ipu,
...@@ -3551,9 +3386,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3551,9 +3386,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__usb_host_hs, &omap44xx_l4_cfg__usb_host_hs,
&omap44xx_l4_cfg__usb_otg_hs, &omap44xx_l4_cfg__usb_otg_hs,
&omap44xx_l4_cfg__usb_tll_hs, &omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_l4_wkup__wd_timer2,
&omap44xx_l4_abe__wd_timer3,
&omap44xx_l4_abe__wd_timer3_dma,
&omap44xx_mpu__emif1, &omap44xx_mpu__emif1,
&omap44xx_mpu__emif2, &omap44xx_mpu__emif2,
&omap44xx_l3_main_2__aes1, &omap44xx_l3_main_2__aes1,
......
This diff is collapsed.
...@@ -62,6 +62,7 @@ void samsung_wdt_reset(void) ...@@ -62,6 +62,7 @@ void samsung_wdt_reset(void)
#ifdef CONFIG_OF #ifdef CONFIG_OF
static const struct of_device_id s3c2410_wdt_match[] = { static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt" }, { .compatible = "samsung,s3c2410-wdt" },
{ .compatible = "samsung,s3c6410-wdt" },
{}, {},
}; };
......
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
# Mvebu SoC Family # Mvebu SoC Family
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
......
This diff is collapsed.
...@@ -215,6 +215,11 @@ spi_quad_pins: spi-quad-pins { ...@@ -215,6 +215,11 @@ spi_quad_pins: spi-quad-pins {
function = "spi"; function = "spi";
}; };
spi_cs1_pins: spi-cs1-pins {
groups = "spi_cs1";
function = "spi";
};
i2c1_pins: i2c1-pins { i2c1_pins: i2c1-pins {
groups = "i2c1"; groups = "i2c1";
function = "i2c"; function = "i2c";
......
...@@ -42,7 +42,7 @@ gic500: interrupt-controller@1800000 { ...@@ -42,7 +42,7 @@ gic500: interrupt-controller@1800000 {
*/ */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@18200000 { gic_its: gic-its@1820000 {
compatible = "arm,gic-v3-its"; compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>; reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>; socionext,synquacer-pre-its = <0x1000000 0x400000>;
...@@ -67,7 +67,7 @@ serdes0: serdes@900000 { ...@@ -67,7 +67,7 @@ serdes0: serdes@900000 {
reg = <0x0 0x900000 0x0 0x2000>; reg = <0x0 0x900000 0x0 0x2000>;
reg-names = "serdes"; reg-names = "serdes";
#phy-cells = <2>; #phy-cells = <2>;
power-domains = <&k3_pds 153>; power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
...@@ -82,7 +82,7 @@ serdes1: serdes@910000 { ...@@ -82,7 +82,7 @@ serdes1: serdes@910000 {
reg = <0x0 0x910000 0x0 0x2000>; reg = <0x0 0x910000 0x0 0x2000>;
reg-names = "serdes"; reg-names = "serdes";
#phy-cells = <2>; #phy-cells = <2>;
power-domains = <&k3_pds 154>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
...@@ -100,7 +100,7 @@ main_uart0: serial@2800000 { ...@@ -100,7 +100,7 @@ main_uart0: serial@2800000 {
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 146>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
}; };
main_uart1: serial@2810000 { main_uart1: serial@2810000 {
...@@ -110,7 +110,7 @@ main_uart1: serial@2810000 { ...@@ -110,7 +110,7 @@ main_uart1: serial@2810000 {
reg-io-width = <4>; reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
power-domains = <&k3_pds 147>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
}; };
main_uart2: serial@2820000 { main_uart2: serial@2820000 {
...@@ -120,7 +120,7 @@ main_uart2: serial@2820000 { ...@@ -120,7 +120,7 @@ main_uart2: serial@2820000 {
reg-io-width = <4>; reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
power-domains = <&k3_pds 148>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
}; };
main_pmx0: pinmux@11c000 { main_pmx0: pinmux@11c000 {
...@@ -147,7 +147,7 @@ main_i2c0: i2c@2000000 { ...@@ -147,7 +147,7 @@ main_i2c0: i2c@2000000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 110 1>; clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
}; };
main_i2c1: i2c@2010000 { main_i2c1: i2c@2010000 {
...@@ -158,7 +158,7 @@ main_i2c1: i2c@2010000 { ...@@ -158,7 +158,7 @@ main_i2c1: i2c@2010000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 111 1>; clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
}; };
main_i2c2: i2c@2020000 { main_i2c2: i2c@2020000 {
...@@ -169,7 +169,7 @@ main_i2c2: i2c@2020000 { ...@@ -169,7 +169,7 @@ main_i2c2: i2c@2020000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 112 1>; clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
}; };
main_i2c3: i2c@2030000 { main_i2c3: i2c@2030000 {
...@@ -180,14 +180,14 @@ main_i2c3: i2c@2030000 { ...@@ -180,14 +180,14 @@ main_i2c3: i2c@2030000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 113 1>; clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
}; };
ecap0: pwm@3100000 { ecap0: pwm@3100000 {
compatible = "ti,am654-ecap", "ti,am3352-ecap"; compatible = "ti,am654-ecap", "ti,am3352-ecap";
#pwm-cells = <3>; #pwm-cells = <3>;
reg = <0x0 0x03100000 0x0 0x60>; reg = <0x0 0x03100000 0x0 0x60>;
power-domains = <&k3_pds 39>; power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>; clocks = <&k3_clks 39 0>;
clock-names = "fck"; clock-names = "fck";
}; };
...@@ -197,7 +197,7 @@ main_spi0: spi@2100000 { ...@@ -197,7 +197,7 @@ main_spi0: spi@2100000 {
reg = <0x0 0x2100000 0x0 0x400>; reg = <0x0 0x2100000 0x0 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 137 1>; clocks = <&k3_clks 137 1>;
power-domains = <&k3_pds 137>; power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -207,7 +207,7 @@ main_spi1: spi@2110000 { ...@@ -207,7 +207,7 @@ main_spi1: spi@2110000 {
reg = <0x0 0x2110000 0x0 0x400>; reg = <0x0 0x2110000 0x0 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 138 1>; clocks = <&k3_clks 138 1>;
power-domains = <&k3_pds 138>; power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>; assigned-clocks = <&k3_clks 137 1>;
...@@ -219,7 +219,7 @@ main_spi2: spi@2120000 { ...@@ -219,7 +219,7 @@ main_spi2: spi@2120000 {
reg = <0x0 0x2120000 0x0 0x400>; reg = <0x0 0x2120000 0x0 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 139 1>; clocks = <&k3_clks 139 1>;
power-domains = <&k3_pds 139>; power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -229,7 +229,7 @@ main_spi3: spi@2130000 { ...@@ -229,7 +229,7 @@ main_spi3: spi@2130000 {
reg = <0x0 0x2130000 0x0 0x400>; reg = <0x0 0x2130000 0x0 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 140 1>; clocks = <&k3_clks 140 1>;
power-domains = <&k3_pds 140>; power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -239,7 +239,7 @@ main_spi4: spi@2140000 { ...@@ -239,7 +239,7 @@ main_spi4: spi@2140000 {
reg = <0x0 0x2140000 0x0 0x400>; reg = <0x0 0x2140000 0x0 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 141 1>; clocks = <&k3_clks 141 1>;
power-domains = <&k3_pds 141>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -247,7 +247,7 @@ main_spi4: spi@2140000 { ...@@ -247,7 +247,7 @@ main_spi4: spi@2140000 {
sdhci0: sdhci@4f80000 { sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1"; compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47>; power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin"; clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
...@@ -306,7 +306,7 @@ dwc3_0: dwc3@4000000 { ...@@ -306,7 +306,7 @@ dwc3_0: dwc3@4000000 {
ranges = <0x0 0x0 0x4000000 0x20000>; ranges = <0x0 0x0 0x4000000 0x20000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent; dma-coherent;
power-domains = <&k3_pds 151>; power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
...@@ -345,7 +345,7 @@ dwc3_1: dwc3@4020000 { ...@@ -345,7 +345,7 @@ dwc3_1: dwc3@4020000 {
ranges = <0x0 0x0 0x4020000 0x20000>; ranges = <0x0 0x0 0x4020000 0x20000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent; dma-coherent;
power-domains = <&k3_pds 152>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 152 2>; assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
...@@ -413,6 +413,12 @@ inta_main_udmass: interrupt-controller@33d00000 { ...@@ -413,6 +413,12 @@ inta_main_udmass: interrupt-controller@33d00000 {
ti,sci-rm-range-vint = <0x0>; ti,sci-rm-range-vint = <0x0>;
ti,sci-rm-range-global-event = <0x1>; ti,sci-rm-range-global-event = <0x1>;
}; };
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
}; };
main_gpio0: main_gpio0@600000 { main_gpio0: main_gpio0@600000 {
...@@ -451,7 +457,7 @@ pcie0_rc: pcie@5500000 { ...@@ -451,7 +457,7 @@ pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc"; compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu"; reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120>; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
...@@ -470,7 +476,7 @@ pcie0_ep: pcie-ep@5500000 { ...@@ -470,7 +476,7 @@ pcie0_ep: pcie-ep@5500000 {
compatible = "ti,am654-pcie-ep"; compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu"; reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120>; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>; ti,syscon-pcie-mode = <&pcie0_mode>;
num-ib-windows = <16>; num-ib-windows = <16>;
num-ob-windows = <16>; num-ob-windows = <16>;
...@@ -483,7 +489,7 @@ pcie1_rc: pcie@5600000 { ...@@ -483,7 +489,7 @@ pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc"; compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu"; reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 121>; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
...@@ -502,7 +508,7 @@ pcie1_ep: pcie-ep@5600000 { ...@@ -502,7 +508,7 @@ pcie1_ep: pcie-ep@5600000 {
compatible = "ti,am654-pcie-ep"; compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu"; reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121>; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>; ti,syscon-pcie-mode = <&pcie1_mode>;
num-ib-windows = <16>; num-ib-windows = <16>;
num-ob-windows = <16>; num-ob-windows = <16>;
......
...@@ -14,7 +14,7 @@ mcu_uart0: serial@40a00000 { ...@@ -14,7 +14,7 @@ mcu_uart0: serial@40a00000 {
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>; clock-frequency = <96000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 149>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
}; };
mcu_ram: sram@41c00000 { mcu_ram: sram@41c00000 {
...@@ -33,7 +33,7 @@ mcu_i2c0: i2c@40b00000 { ...@@ -33,7 +33,7 @@ mcu_i2c0: i2c@40b00000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 114 1>; clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
}; };
mcu_spi0: spi@40300000 { mcu_spi0: spi@40300000 {
...@@ -41,7 +41,7 @@ mcu_spi0: spi@40300000 { ...@@ -41,7 +41,7 @@ mcu_spi0: spi@40300000 {
reg = <0x0 0x40300000 0x0 0x400>; reg = <0x0 0x40300000 0x0 0x400>;
interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 142 1>; clocks = <&k3_clks 142 1>;
power-domains = <&k3_pds 142>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -51,7 +51,7 @@ mcu_spi1: spi@40310000 { ...@@ -51,7 +51,7 @@ mcu_spi1: spi@40310000 {
reg = <0x0 0x40310000 0x0 0x400>; reg = <0x0 0x40310000 0x0 0x400>;
interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 143 1>; clocks = <&k3_clks 143 1>;
power-domains = <&k3_pds 143>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
...@@ -61,7 +61,7 @@ mcu_spi2: spi@40320000 { ...@@ -61,7 +61,7 @@ mcu_spi2: spi@40320000 {
reg = <0x0 0x40320000 0x0 0x400>; reg = <0x0 0x40320000 0x0 0x400>;
interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 144 1>; clocks = <&k3_clks 144 1>;
power-domains = <&k3_pds 144>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
}; };
......
...@@ -20,7 +20,7 @@ dmsc: dmsc { ...@@ -20,7 +20,7 @@ dmsc: dmsc {
k3_pds: power-controller { k3_pds: power-controller {
compatible = "ti,sci-pm-domain"; compatible = "ti,sci-pm-domain";
#power-domain-cells = <1>; #power-domain-cells = <2>;
}; };
k3_clks: clocks { k3_clks: clocks {
...@@ -50,7 +50,7 @@ wkup_uart0: serial@42300000 { ...@@ -50,7 +50,7 @@ wkup_uart0: serial@42300000 {
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 150>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
}; };
wkup_i2c0: i2c@42120000 { wkup_i2c0: i2c@42120000 {
...@@ -61,7 +61,7 @@ wkup_i2c0: i2c@42120000 { ...@@ -61,7 +61,7 @@ wkup_i2c0: i2c@42120000 {
#size-cells = <0>; #size-cells = <0>;
clock-names = "fck"; clock-names = "fck";
clocks = <&k3_clks 115 1>; clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
}; };
intr_wkup_gpio: interrupt-controller2 { intr_wkup_gpio: interrupt-controller2 {
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ { / {
model = "Texas Instruments K3 AM654 SoC"; model = "Texas Instruments K3 AM654 SoC";
......
...@@ -151,6 +151,7 @@ &wkup_uart0 { ...@@ -151,6 +151,7 @@ &wkup_uart0 {
&main_uart0 { &main_uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>; pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
}; };
&wkup_i2c0 { &wkup_i2c0 {
......
...@@ -6,12 +6,49 @@ ...@@ -6,12 +6,49 @@
/dts-v1/; /dts-v1/;
#include "k3-j721e-som-p0.dtsi" #include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ { / {
chosen { chosen {
stdout-path = "serial2:115200n8"; stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
}; };
gpio_keys: gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
sw10: sw10 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
};
sw11: sw11 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
};
};
};
&main_pmx0 {
sw10_button_pins_default: sw10_button_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
>;
};
};
&wkup_pmx0 {
sw11_button_pins_default: sw11_button_pins_default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
>;
};
}; };
&wkup_uart0 { &wkup_uart0 {
...@@ -19,6 +56,10 @@ &wkup_uart0 { ...@@ -19,6 +56,10 @@ &wkup_uart0 {
status = "disabled"; status = "disabled";
}; };
&main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_uart3 { &main_uart3 {
/* UART not brought out */ /* UART not brought out */
status = "disabled"; status = "disabled";
...@@ -48,3 +89,31 @@ &main_uart9 { ...@@ -48,3 +89,31 @@ &main_uart9 {
/* UART not brought out */ /* UART not brought out */
status = "disabled"; status = "disabled";
}; };
&main_gpio2 {
status = "disabled";
};
&main_gpio3 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio5 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&main_gpio7 {
status = "disabled";
};
&wkup_gpio1 {
status = "disabled";
};
...@@ -31,7 +31,7 @@ gic500: interrupt-controller@1800000 { ...@@ -31,7 +31,7 @@ gic500: interrupt-controller@1800000 {
/* vcpumntirq: virtual CPU interface maintenance interrupt */ /* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@18200000 { gic_its: gic-its@1820000 {
compatible = "arm,gic-v3-its"; compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>; reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>; socionext,synquacer-pre-its = <0x1000000 0x400000>;
...@@ -89,6 +89,12 @@ main_udmass_inta: interrupt-controller@33d00000 { ...@@ -89,6 +89,12 @@ main_udmass_inta: interrupt-controller@33d00000 {
ti,sci-rm-range-vint = <0xa>; ti,sci-rm-range-vint = <0xa>;
ti,sci-rm-range-global-event = <0xd>; ti,sci-rm-range-global-event = <0xd>;
}; };
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
}; };
secure_proxy_main: mailbox@32c00000 { secure_proxy_main: mailbox@32c00000 {
...@@ -119,7 +125,7 @@ main_uart0: serial@2800000 { ...@@ -119,7 +125,7 @@ main_uart0: serial@2800000 {
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 146>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>; clocks = <&k3_clks 146 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -132,7 +138,7 @@ main_uart1: serial@2810000 { ...@@ -132,7 +138,7 @@ main_uart1: serial@2810000 {
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 278>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>; clocks = <&k3_clks 278 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -145,7 +151,7 @@ main_uart2: serial@2820000 { ...@@ -145,7 +151,7 @@ main_uart2: serial@2820000 {
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 279>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>; clocks = <&k3_clks 279 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -158,7 +164,7 @@ main_uart3: serial@2830000 { ...@@ -158,7 +164,7 @@ main_uart3: serial@2830000 {
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 280>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>; clocks = <&k3_clks 280 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -171,7 +177,7 @@ main_uart4: serial@2840000 { ...@@ -171,7 +177,7 @@ main_uart4: serial@2840000 {
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 281>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>; clocks = <&k3_clks 281 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -184,7 +190,7 @@ main_uart5: serial@2850000 { ...@@ -184,7 +190,7 @@ main_uart5: serial@2850000 {
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 282>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>; clocks = <&k3_clks 282 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -197,7 +203,7 @@ main_uart6: serial@2860000 { ...@@ -197,7 +203,7 @@ main_uart6: serial@2860000 {
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 283>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>; clocks = <&k3_clks 283 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -210,7 +216,7 @@ main_uart7: serial@2870000 { ...@@ -210,7 +216,7 @@ main_uart7: serial@2870000 {
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 284>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>; clocks = <&k3_clks 284 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -223,7 +229,7 @@ main_uart8: serial@2880000 { ...@@ -223,7 +229,7 @@ main_uart8: serial@2880000 {
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 285>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>; clocks = <&k3_clks 285 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -236,8 +242,140 @@ main_uart9: serial@2890000 { ...@@ -236,8 +242,140 @@ main_uart9: serial@2890000 {
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 286>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>; clocks = <&k3_clks 286 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
<105 4>, <105 5>, <105 6>, <105 7>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <128>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <106 0>, <106 1>, <106 2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <36>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 0>;
clock-names = "gpio";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00610000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
<107 4>, <107 5>, <107 6>, <107 7>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <128>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
};
main_gpio3: gpio@611000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00611000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <108 0>, <108 1>, <108 2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <36>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 108 0>;
clock-names = "gpio";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00620000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
<109 4>, <109 5>, <109 6>, <109 7>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <128>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
};
main_gpio5: gpio@621000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00621000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <110 0>, <110 1>, <110 2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <36>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 110 0>;
clock-names = "gpio";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00630000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
<111 4>, <111 5>, <111 6>, <111 7>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <128>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
};
main_gpio7: gpio@631000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x00631000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <112 0>, <112 1>, <112 2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <36>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
};
}; };
...@@ -20,7 +20,7 @@ dmsc: dmsc@44083000 { ...@@ -20,7 +20,7 @@ dmsc: dmsc@44083000 {
k3_pds: power-controller { k3_pds: power-controller {
compatible = "ti,sci-pm-domain"; compatible = "ti,sci-pm-domain";
#power-domain-cells = <1>; #power-domain-cells = <2>;
}; };
k3_clks: clocks { k3_clks: clocks {
...@@ -59,7 +59,7 @@ wkup_uart0: serial@42300000 { ...@@ -59,7 +59,7 @@ wkup_uart0: serial@42300000 {
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 287>; power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>; clocks = <&k3_clks 287 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -72,7 +72,7 @@ mcu_uart0: serial@40a00000 { ...@@ -72,7 +72,7 @@ mcu_uart0: serial@40a00000 {
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>; clock-frequency = <96000000>;
current-speed = <115200>; current-speed = <115200>;
power-domains = <&k3_pds 149>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>; clocks = <&k3_clks 149 0>;
clock-names = "fclk"; clock-names = "fclk";
}; };
...@@ -87,4 +87,38 @@ wkup_gpio_intr: interrupt-controller2 { ...@@ -87,4 +87,38 @@ wkup_gpio_intr: interrupt-controller2 {
ti,sci-dst-id = <14>; ti,sci-dst-id = <14>;
ti,sci-rm-range-girq = <0x5>; ti,sci-rm-range-girq = <0x5>;
}; };
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x42110000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <113 0>, <113 1>, <113 2>,
<113 3>, <113 4>, <113 5>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <84>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
wkup_gpio1: gpio@42100000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x42100000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <114 0>, <114 1>, <114 2>,
<114 3>, <114 4>, <114 5>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <84>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
};
}; };
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ { / {
model = "Texas Instruments K3 J721E SoC"; model = "Texas Instruments K3 J721E SoC";
......
This diff is collapsed.
...@@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = ...@@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst =
{ 0 }, { 0 },
}; };
static const char * const omap5_gpu_core_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
NULL,
};
static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
NULL,
};
static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
"sys_clkin",
NULL,
};
static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
{ 0 },
};
static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
"func_128m_clk", "func_128m_clk",
"dpll_per_m2x2_ck", "dpll_per_m2x2_ck",
...@@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { ...@@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
{ 0x4a008e20, omap5_l3instr_clkctrl_regs }, { 0x4a008e20, omap5_l3instr_clkctrl_regs },
{ 0x4a009020, omap5_l4per_clkctrl_regs }, { 0x4a009020, omap5_l4per_clkctrl_regs },
{ 0x4a009420, omap5_dss_clkctrl_regs }, { 0x4a009420, omap5_dss_clkctrl_regs },
{ 0x4a009520, omap5_gpu_clkctrl_regs },
{ 0x4a009620, omap5_l3init_clkctrl_regs }, { 0x4a009620, omap5_l3init_clkctrl_regs },
{ 0x4ae07920, omap5_wkupaon_clkctrl_regs }, { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
{ 0 }, { 0 },
......
/* SPDX-License-Identifier: GPL-2.0 */
/* TI sysc interconnect target module defines */ /* TI sysc interconnect target module defines */
/* Generic sysc found on omap2 and later, also known as type1 */ /* Generic sysc found on omap2 and later, also known as type1 */
......
...@@ -89,6 +89,9 @@ ...@@ -89,6 +89,9 @@
/* dss clocks */ /* dss clocks */
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* gpu clocks */
#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* l3init clocks */ /* l3init clocks */
#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
......
...@@ -32,4 +32,7 @@ ...@@ -32,4 +32,7 @@
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#endif #endif
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