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Commit f97ee3e9 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-arm-dt-for-v5.16-tag2' of... 

Merge tag 'renesas-arm-dt-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.16 (take two)

  - SPI Multi I/O Bus, SDHI, and Ethernet support for the RZ/G2L SoC,
  - SPI Multi I/O Bus, camera, and video-on support for the R-Car V3U
    SoC,
  - SPI FLASH support for the Falcon development board,
  - eMMC, microSD, and Ethernet support for the RZ/G2L SMARC EVK
    development board,
  - 2 GHz High-Performance support for the R-Car H3e-2G, M3e-2G, and
    M3Ne-2G SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  mailmap: Fix text encoding for Niklas Söderlund
  arm64: dts: renesas: rcar-gen3e: Add Cortex-A57 2 GHz opps
  arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet
  arm64: dts: renesas: r9a07g044: Add GbEthernet nodes
  arm64: dts: renesas: Add ports node to all adv7482 nodes
  arm64: dts: renesas: r8a779a0: Add and connect all CSI-2, ISP and VIN nodes
  arm64: dts: renesas: rzg2l-smarc: Enable microSD on SMARC platform
  arm64: dts: renesas: rzg2l-smarc-som: Enable eMMC on SMARC platform
  arm64: dts: renesas: r9a07g044: Add SDHI nodes
  arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC
  arm64: dts: renesas: r8a779a0: Add RPC node
  arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller node

Link: https://lore.kernel.org/r/cover.1634298094.git.geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f6bfe014 6be85db4
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.mailmap
View file @ f97ee3e9
......@@ -276,6 +276,7 @@ Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>
Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.com>
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
Oleksij Rempel <linux@rempel-privat.de> <fixed-term.Oleksij.Rempel@de.bosch.com>
......
arch/arm64/boot/dts/renesas/ebisu.dtsi
View file @ f97ee3e9
......@@ -423,37 +423,39 @@ video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupt-names = "intrq1", "intrq2";
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
<17 IRQ_TYPE_LEVEL_LOW>;
port@7 {
reg = <7>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
};
port@8 {
reg = <8>;
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
};
port@a {
reg = <10>;
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
......
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
View file @ f97ee3e9
......@@ -203,6 +203,11 @@ mmc_pins: mmc {
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
......@@ -214,6 +219,34 @@ scif_clk_pins: scif_clk {
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0xcc0000>;
read-only;
};
user@cc0000 {
reg = <0xcc0000 0x3340000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file @ f97ee3e9
This diff is collapsed.
arch/arm64/boot/dts/renesas/r8a779m1.dtsi
View file @ f97ee3e9
......@@ -10,3 +10,12 @@
/ {
compatible = "renesas,r8a779m1", "renesas,r8a7795";
};
&cluster0_opp {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
arch/arm64/boot/dts/renesas/r8a779m3.dtsi
View file @ f97ee3e9
......@@ -10,3 +10,12 @@
/ {
compatible = "renesas,r8a779m3", "renesas,r8a77961";
};
&cluster0_opp {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
arch/arm64/boot/dts/renesas/r8a779m5.dtsi
View file @ f97ee3e9
......@@ -10,3 +10,12 @@
/ {
compatible = "renesas,r8a779m5", "renesas,r8a77965";
};
&cluster0_opp {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View file @ f97ee3e9
......@@ -358,6 +358,23 @@ channel@7 {
};
};
sbc: spi@10060000 {
compatible = "renesas,r9a07g044-rpc-if",
"renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
<&cpg CPG_MOD R9A07G044_SPI_CLK>;
resets = <&cpg R9A07G044_SPI_RST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
......@@ -439,6 +456,78 @@ gic: interrupt-controller@11900000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g044",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
resets = <&cpg R9A07G044_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g044",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
resets = <&cpg R9A07G044_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g044-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
<&cpg CPG_CORE R9A07G044_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g044-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
<&cpg CPG_CORE R9A07G044_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {
compatible = "renesas,r9a07g044-usbphy-ctrl",
"renesas,rzg2l-usbphy-ctrl";
......
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View file @ f97ee3e9
......@@ -5,14 +5,64 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
#define EMMC 1
/*
* To enable uSD card on CN3,
* SW1[2] should be at position 3/ON.
* Disable eMMC by setting "#define EMMC 0" above.
*/
#define SDHI (!EMMC)
/ {
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <3300000 1>, <1800000 0>;
regulator-boot-on;
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
};
&adc {
......@@ -24,6 +74,58 @@ &adc {
/delete-node/ channel@7;
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
......@@ -32,4 +134,142 @@ &pinctrl {
adc_pins: adc {
pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
};
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
};
gpio-sd0-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_pwr_en";
};
/*
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
* The below switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
* SW1[2] should be at position 2/OFF to enable 64 GB eMMC
* SW1[2] should be at position 3/ON to enable uSD card CN3
*/
sd0-dev-sel-hog {
gpio-hog;
gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd0_dev_sel";
};
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
};
#if SDHI
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
#endif
#if EMMC
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
View file @ f97ee3e9
......@@ -30,7 +30,6 @@ aliases {
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
......@@ -70,6 +69,16 @@ usb0_vbus_otg: regulator-usb0-vbus-otg {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
};
&audio_clk1{
......@@ -199,6 +208,45 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
......@@ -229,6 +277,19 @@ &scif0 {
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi1>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
......
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file @ f97ee3e9
......@@ -526,47 +526,49 @@ video-receiver@70 {
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio6>;
interrupt-names = "intrq1", "intrq2";
interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
port@7 {
reg = <7>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
};
port@8 {
reg = <8>;
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
};
port@a {
reg = <10>;
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
port@b {
reg = <11>;
port@b {
reg = <11>;
adv7482_txb: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&csi20_in>;
adv7482_txb: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&csi20_in>;
};
};
};
};
......
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