Commit f99d3023 authored by Ralf Baechle's avatar Ralf Baechle

Sprinkle a few more .set mipsX over xchg to make sure we dont' end up with

64-bit instructions on 32-bit processors, they tend to be unhappy about
that kind of food ;-)
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e607d6c8
...@@ -302,7 +302,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, ...@@ -302,7 +302,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
" .set mips3 \n" " .set mips3 \n"
"1: ll %0, %2 # __cmpxchg_u32 \n" "1: ll %0, %2 # __cmpxchg_u32 \n"
" bne %0, %z3, 2f \n" " bne %0, %z3, 2f \n"
" .set mips0 \n"
" move $1, %z4 \n" " move $1, %z4 \n"
" .set mips3 \n"
" sc $1, %1 \n" " sc $1, %1 \n"
" beqzl $1, 1b \n" " beqzl $1, 1b \n"
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
...@@ -320,7 +322,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, ...@@ -320,7 +322,9 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
" .set mips3 \n" " .set mips3 \n"
"1: ll %0, %2 # __cmpxchg_u32 \n" "1: ll %0, %2 # __cmpxchg_u32 \n"
" bne %0, %z3, 2f \n" " bne %0, %z3, 2f \n"
" .set mips0 \n"
" move $1, %z4 \n" " move $1, %z4 \n"
" .set mips3 \n"
" sc $1, %1 \n" " sc $1, %1 \n"
" beqz $1, 1b \n" " beqz $1, 1b \n"
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
......
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