Commit f9bde19b authored by Jeff Garzik's avatar Jeff Garzik

[IA32] VIA C3 crypto/RNG bits

* Enable ACE (crypto) and RNG units on bootup.
* Do not disable RNG unit when unloading hw_random module.
* New bits listed in /proc/cpuinfo: rng_en, ace, ace_en
* Add ACE-associated constants to cpufeature.h
parent 0dc316de
...@@ -246,7 +246,15 @@ static void __init winchip2_protect_mcr(void) ...@@ -246,7 +246,15 @@ static void __init winchip2_protect_mcr(void)
lo&=~0x1C0; /* blank bits 8-6 */ lo&=~0x1C0; /* blank bits 8-6 */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi); wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
} }
#endif #endif /* CONFIG_X86_OOSTORE */
#define ACE_PRESENT (1 << 6)
#define ACE_ENABLED (1 << 7)
#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
#define RNG_PRESENT (1 << 2)
#define RNG_ENABLED (1 << 3)
#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
static void __init init_c3(struct cpuinfo_x86 *c) static void __init init_c3(struct cpuinfo_x86 *c)
{ {
...@@ -254,6 +262,24 @@ static void __init init_c3(struct cpuinfo_x86 *c) ...@@ -254,6 +262,24 @@ static void __init init_c3(struct cpuinfo_x86 *c)
/* Test for Centaur Extended Feature Flags presence */ /* Test for Centaur Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) { if (cpuid_eax(0xC0000000) >= 0xC0000001) {
u32 tmp = cpuid_edx(0xC0000001);
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
rdmsr (MSR_VIA_FCR, lo, hi);
lo |= ACE_FCR; /* enable ACE unit */
wrmsr (MSR_VIA_FCR, lo, hi);
printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
}
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
rdmsr (MSR_VIA_RNG, lo, hi);
lo |= RNG_ENABLE; /* enable RNG unit */
wrmsr (MSR_VIA_RNG, lo, hi);
printk(KERN_INFO "CPU: Enabled h/w RNG\n");
}
/* store Centaur Extended Feature Flags as /* store Centaur Extended Feature Flags as
* word 5 of the CPU capability bit array * word 5 of the CPU capability bit array
*/ */
......
...@@ -50,7 +50,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -50,7 +50,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/* VIA/Cyrix/Centaur-defined */ /* VIA/Cyrix/Centaur-defined */
NULL, NULL, "xstore", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
......
...@@ -454,11 +454,7 @@ static int __init via_init(struct pci_dev *dev) ...@@ -454,11 +454,7 @@ static int __init via_init(struct pci_dev *dev)
static void via_cleanup(void) static void via_cleanup(void)
{ {
u32 lo, hi; /* do nothing */
rdmsr(MSR_VIA_RNG, lo, hi);
lo &= ~VIA_RNG_ENABLE;
wrmsr(MSR_VIA_RNG, lo, hi);
} }
......
...@@ -76,6 +76,9 @@ ...@@ -76,6 +76,9 @@
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
...@@ -101,6 +104,7 @@ ...@@ -101,6 +104,7 @@
#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
#endif /* __ASM_I386_CPUFEATURE_H */ #endif /* __ASM_I386_CPUFEATURE_H */
......
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