drm/amd/display: roll back quality EASF and ISHARP and dc dependency changes

[Why]
Seeing several regressions related to quality EASF and ISHARP changes
and removing dc dependency changes.

[How]
Roll back SPL changes
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

@@ -1511,6 +1511,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
 
 		pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
+		spl_out->scl_data.h_active = pipe_ctx->plane_res.scl_data.h_active;
+		spl_out->scl_data.v_active = pipe_ctx->plane_res.scl_data.v_active;
 
 		// Convert pipe_ctx to respective input params for SPL
 		translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

@@ -42,26 +42,26 @@ static void populate_spltaps_from_taps(struct spl_taps *spl_scaling_quality,
 static void populate_taps_from_spltaps(struct scaling_taps *scaling_quality,
 		const struct spl_taps *spl_scaling_quality)
 {
-	scaling_quality->h_taps_c = spl_scaling_quality->h_taps_c + 1;
-	scaling_quality->h_taps = spl_scaling_quality->h_taps + 1;
-	scaling_quality->v_taps_c = spl_scaling_quality->v_taps_c + 1;
-	scaling_quality->v_taps = spl_scaling_quality->v_taps + 1;
+	scaling_quality->h_taps_c = spl_scaling_quality->h_taps_c;
+	scaling_quality->h_taps = spl_scaling_quality->h_taps;
+	scaling_quality->v_taps_c = spl_scaling_quality->v_taps_c;
+	scaling_quality->v_taps = spl_scaling_quality->v_taps;
 }
 static void populate_ratios_from_splratios(struct scaling_ratios *ratios,
-		const struct ratio *spl_ratios)
+		const struct spl_ratios *spl_ratios)
 {
-	ratios->horz = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio >> 5, 3, 19);
-	ratios->vert = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio >> 5, 3, 19);
-	ratios->horz_c = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio_c >> 5, 3, 19);
-	ratios->vert_c = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio_c >> 5, 3, 19);
+	ratios->horz = spl_ratios->horz;
+	ratios->vert = spl_ratios->vert;
+	ratios->horz_c = spl_ratios->horz_c;
+	ratios->vert_c = spl_ratios->vert_c;
 }
 static void populate_inits_from_splinits(struct scl_inits *inits,
-		const struct init *spl_inits)
+		const struct spl_inits *spl_inits)
 {
-	inits->h = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int, spl_inits->h_filter_init_frac >> 5, 0, 19);
-	inits->v = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int, spl_inits->v_filter_init_frac >> 5, 0, 19);
-	inits->h_c = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int_c, spl_inits->h_filter_init_frac_c >> 5, 0, 19);
-	inits->v_c = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int_c, spl_inits->v_filter_init_frac_c >> 5, 0, 19);
+	inits->h = spl_inits->h;
+	inits->v = spl_inits->v;
+	inits->h_c = spl_inits->h_c;
+	inits->v_c = spl_inits->v_c;
 }
 /// @brief Translate SPL input parameters from pipe context
 /// @param pipe_ctx
@@ -170,15 +170,6 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
 	/* Translate transfer function */
 	spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type;
 	spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf;
-
-	spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active;
-	spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active;
-	/* Check if it is stream is in fullscreen and if its HDR.
-	 * Use this to determine sharpness levels
-	 */
-	spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream);
-	spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);
-
 }
 
 /// @brief Translate SPL output parameters to pipe context
@@ -187,15 +178,15 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
 void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out)
 {
 	// Make scaler data recout point to spl output field recout
-	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout);
+	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->scl_data.recout);
 	// Make scaler data ratios point to spl output field ratios
-	populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios);
+	populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->scl_data.ratios);
 	// Make scaler data viewport point to spl output field viewport
-	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport);
+	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->scl_data.viewport);
 	// Make scaler data viewport_c point to spl output field viewport_c
-	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c);
+	populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->scl_data.viewport_c);
 	// Make scaler data taps point to spl output field scaling taps
-	populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps);
+	populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->scl_data.taps);
 	// Make scaler data init point to spl output field init
-	populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init);
+	populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->scl_data.inits);
 }

drivers/gpu/drm/amd/display/dc/dc_spl_translate.h

@@ -6,7 +6,6 @@
 #define __DC_SPL_TRANSLATE_H__
 #include "dc.h"
 #include "resource.h"
-#include "dm_helpers.h"
 
 /* Map SPL input parameters to pipe context
  * @pipe_ctx: pipe context

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

@@ -788,14 +788,6 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
 		 * certain cases. Hence do corrective active and disable scaling.
 		 */
 		plane->composition.scaler_info.enabled = false;
-	} else if ((plane_state->ctx->dc->config.use_spl == true) &&
-		(plane->composition.scaler_info.enabled == false)) {
-		/* To enable sharpener for 1:1, scaler must be enabled.  If use_spl is set, then
-		 *  allow case where ratio is 1 but taps > 1
-		 */
-		if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) ||
-			(scaler_data->taps.h_taps_c > 1) || (scaler_data->taps.v_taps_c > 1))
-			plane->composition.scaler_info.enabled = true;
 	}
 
 	/* always_scale is only used for debug purposes not used in production but has to be

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

@@ -76,9 +76,6 @@
 
 #include "dml2/dml2_wrapper.h"
 
-#include "spl/dc_spl_scl_easf_filters.h"
-#include "spl/dc_spl_isharp_filters.h"
-
 #define DC_LOGGER_INIT(logger)
 
 enum dcn401_clk_src_array_id {
@@ -2126,10 +2123,6 @@ static bool dcn401_resource_construct(
 	dc->dml2_options.max_segments_per_hubp = 20;
 	dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
 
-	/* SPL */
-	spl_init_easf_filter_coeffs();
-	spl_init_blur_scale_coeffs();
-
 	return true;
 
 create_fail:

drivers/gpu/drm/amd/display/dc/spl/Makefile

@@ -23,7 +23,7 @@
 # Makefile for the 'spl' sub-component of DAL.
 # It provides the scaling library interface.
 
-SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o
+SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_filters_old.o dc_spl_isharp_filters.o
 
 AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/spl/,$(SPL))
 

drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c

-// SPDX-License-Identifier: MIT
-//
-// Copyright 2024 Advanced Micro Devices, Inc.
-
-#include "dc_spl_filters.h"
-
-void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,
-	uint16_t *s1_12_filter, int num_taps)
-{
-	int num_entries = NUM_PHASES_COEFF * num_taps;
-	int i;
-
-	for (i = 0; i < num_entries; i++)
-		*(s1_12_filter + i) = *(s1_10_filter + i) * 4;
-}

drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h

-/* SPDX-License-Identifier: MIT */
-
-/* Copyright 2024 Advanced Micro Devices, Inc. */
-
-#ifndef __DC_SPL_FILTERS_H__
-#define __DC_SPL_FILTERS_H__
-
-#include "dc_spl_types.h"
-
-#define NUM_PHASES_COEFF 33
-
-void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,
-	uint16_t *s1_12_filter, int num_taps);
-
-#endif /* __DC_SPL_FILTERS_H__ */

drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h

@@ -12,37 +12,6 @@ const uint32_t *spl_get_filter_isharp_1D_lut_0p5x(void);
 const uint32_t *spl_get_filter_isharp_1D_lut_1p0x(void);
 const uint32_t *spl_get_filter_isharp_1D_lut_1p5x(void);
 const uint32_t *spl_get_filter_isharp_1D_lut_2p0x(void);
-const uint32_t *spl_get_filter_isharp_1D_lut_3p0x(void);
-uint16_t *spl_get_filter_isharp_bs_4tap_in_6_64p(void);
-uint16_t *spl_get_filter_isharp_bs_4tap_64p(void);
-uint16_t *spl_get_filter_isharp_bs_3tap_64p(void);
+const uint16_t *spl_get_filter_isharp_bs_4tap_64p(void);
 const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void);
-uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps);
-
-struct scale_ratio_to_sharpness_level_lookup {
-	unsigned int ratio_numer;
-	unsigned int ratio_denom;
-	unsigned int sharpness_numer;
-	unsigned int sharpness_denom;
-};
-
-struct sharpness_level_mapping {
-	unsigned int level;
-	unsigned int level_numer;
-	unsigned int level_denom;
-};
-
-enum system_setup {
-	SDR_NL = 0,
-	SDR_L,
-	HDR_NL,
-	HDR_L
-};
-
-void spl_init_blur_scale_coeffs(void);
-void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,
-	const struct spl_scaler_data *data);
-
-void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup);
-uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum explicit_sharpness sharpness);
 #endif /* __DC_SPL_ISHARP_FILTERS_H__ */

drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h

-/* SPDX-License-Identifier: MIT */
-
-/* Copyright 2024 Advanced Micro Devices, Inc. */
-
-#ifndef __DC_SPL_SCL_EASF_FILTERS_H__
-#define __DC_SPL_SCL_EASF_FILTERS_H__
-
-#include "dc_spl_types.h"
-
-struct scale_ratio_to_reg_value_lookup {
-	int numer;
-	int denom;
-	const uint32_t reg_value;
-};
-
-void spl_init_easf_filter_coeffs(void);
-uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio);
-uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio);
-uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio);
-uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio);
-void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,
-	const struct spl_scaler_data *data, bool enable_easf_v,
-	bool enable_easf_h);
-
-uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio);
-uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio);
-uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio);
-uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio);
-
-#endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */

drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h

@@ -7,16 +7,53 @@
 
 #include "dc_spl_types.h"
 
-const uint16_t *spl_get_filter_3tap_16p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_4tap_16p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio);
-const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio);
+const uint16_t *spl_get_filter_3tap_16p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_3tap_64p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_4tap_16p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_4tap_64p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_5tap_64p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_6tap_64p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_7tap_64p(struct fixed31_32 ratio);
+const uint16_t *spl_get_filter_8tap_64p(struct fixed31_32 ratio);
 const uint16_t *spl_get_filter_2tap_16p(void);
 const uint16_t *spl_get_filter_2tap_64p(void);
-const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio);
+const uint16_t *spl_get_filter_3tap_16p_upscale(void);
+const uint16_t *spl_get_filter_3tap_16p_116(void);
+const uint16_t *spl_get_filter_3tap_16p_149(void);
+const uint16_t *spl_get_filter_3tap_16p_183(void);
 
+const uint16_t *spl_get_filter_4tap_16p_upscale(void);
+const uint16_t *spl_get_filter_4tap_16p_116(void);
+const uint16_t *spl_get_filter_4tap_16p_149(void);
+const uint16_t *spl_get_filter_4tap_16p_183(void);
+
+const uint16_t *spl_get_filter_3tap_64p_upscale(void);
+const uint16_t *spl_get_filter_3tap_64p_116(void);
+const uint16_t *spl_get_filter_3tap_64p_149(void);
+const uint16_t *spl_get_filter_3tap_64p_183(void);
+
+const uint16_t *spl_get_filter_4tap_64p_upscale(void);
+const uint16_t *spl_get_filter_4tap_64p_116(void);
+const uint16_t *spl_get_filter_4tap_64p_149(void);
+const uint16_t *spl_get_filter_4tap_64p_183(void);
+
+const uint16_t *spl_get_filter_5tap_64p_upscale(void);
+const uint16_t *spl_get_filter_5tap_64p_116(void);
+const uint16_t *spl_get_filter_5tap_64p_149(void);
+const uint16_t *spl_get_filter_5tap_64p_183(void);
+
+const uint16_t *spl_get_filter_6tap_64p_upscale(void);
+const uint16_t *spl_get_filter_6tap_64p_116(void);
+const uint16_t *spl_get_filter_6tap_64p_149(void);
+const uint16_t *spl_get_filter_6tap_64p_183(void);
+
+const uint16_t *spl_get_filter_7tap_64p_upscale(void);
+const uint16_t *spl_get_filter_7tap_64p_116(void);
+const uint16_t *spl_get_filter_7tap_64p_149(void);
+const uint16_t *spl_get_filter_7tap_64p_183(void);
+
+const uint16_t *spl_get_filter_8tap_64p_upscale(void);
+const uint16_t *spl_get_filter_8tap_64p_116(void);
+const uint16_t *spl_get_filter_8tap_64p_149(void);
+const uint16_t *spl_get_filter_8tap_64p_183(void);
 #endif /* __DC_SPL_SCL_FILTERS_H__ */

drivers/gpu/drm/amd/display/dc/spl/spl_debug.h

-/* Copyright  1997-2004 Advanced Micro Devices, Inc. All rights reserved. */
-
-#ifndef SPL_DEBUG_H
-#define SPL_DEBUG_H
-
-#ifdef SPL_ASSERT
-#undef SPL_ASSERT
-#endif
-#define SPL_ASSERT(b)
-
-#define SPL_ASSERT_CRITICAL(expr)  do {if (expr)/* Do nothing */; } while (0)
-
-#ifdef SPL_DALMSG
-#undef SPL_DALMSG
-#endif
-#define SPL_DALMSG(b)
-
-#ifdef SPL_DAL_ASSERT_MSG
-#undef SPL_DAL_ASSERT_MSG
-#endif
-#define SPL_DAL_ASSERT_MSG(b, m)
-
-#endif  // SPL_DEBUG_H