Commit fa082a7c authored by Kate Hsuan's avatar Kate Hsuan Committed by Hans de Goede

platform/x86: intel_pmc_core: Move to intel sub-directory

Move Intel PMC core driver to intel sub-directory to improve readability.
Signed-off-by: default avatarKate Hsuan <hpa@redhat.com>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarRajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20210820110458.73018-7-andriy.shevchenko@linux.intel.comSigned-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 386d17b2
......@@ -9483,7 +9483,7 @@ M: David E Box <david.e.box@intel.com>
L: platform-driver-x86@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-platform-intel-pmc
F: drivers/platform/x86/intel_pmc_core*
F: drivers/platform/x86/intel/pmc/
INTEL PMIC GPIO DRIVERS
M: Andy Shevchenko <andy@kernel.org>
......
......@@ -1159,27 +1159,6 @@ config INTEL_UNCORE_FREQ_CONTROL
To compile this driver as a module, choose M here: the module
will be called intel-uncore-frequency.
config INTEL_PMC_CORE
tristate "Intel PMC Core driver"
depends on PCI
depends on ACPI
help
The Intel Platform Controller Hub for Intel Core SoCs provides access
to Power Management Controller registers via various interfaces. This
driver can utilize debugging capabilities and supported features as
exposed by the Power Management Controller. It also may perform some
tasks in the PMC in order to enable transition into the SLPS0 state.
It should be selected on all Intel platforms supported by the driver.
Supported features:
- SLP_S0_RESIDENCY counter
- PCH IP Power Gating status
- LTR Ignore / LTR Show
- MPHY/PLL gating status (Sunrisepoint PCH only)
- SLPS0 Debug registers (Cannonlake/Icelake PCH)
- Low Power Mode registers (Tigerlake and beyond)
- PMC quirks as needed to enable SLPS0/S0ix
config INTEL_SCU_IPC
bool
......
......@@ -127,7 +127,6 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o
# Intel PMIC / PMC / P-Unit devices
obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv.o
obj-$(CONFIG_INTEL_SCU_IPC) += intel_scu_ipc.o
obj-$(CONFIG_INTEL_SCU_PCI) += intel_scu_pcidrv.o
obj-$(CONFIG_INTEL_SCU_PLATFORM) += intel_scu_pltdrv.o
......
......@@ -19,6 +19,7 @@ if X86_PLATFORM_DRIVERS_INTEL
source "drivers/platform/x86/intel/int1092/Kconfig"
source "drivers/platform/x86/intel/int33fe/Kconfig"
source "drivers/platform/x86/intel/int3472/Kconfig"
source "drivers/platform/x86/intel/pmc/Kconfig"
source "drivers/platform/x86/intel/pmt/Kconfig"
config INTEL_BXTWC_PMIC_TMU
......
......@@ -7,6 +7,7 @@
obj-$(CONFIG_INTEL_SAR_INT1092) += int1092/
obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/
obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/
obj-$(CONFIG_INTEL_PMC_CORE) += pmc/
obj-$(CONFIG_INTEL_PMT_CLASS) += pmt/
# Intel PMIC / PMC / P-Unit drivers
......
# SPDX-License-Identifier: GPL-2.0
#
# Intel x86 Platform-Specific Drivers
#
config INTEL_PMC_CORE
tristate "Intel PMC Core driver"
depends on PCI
depends on ACPI
help
The Intel Platform Controller Hub for Intel Core SoCs provides access
to Power Management Controller registers via various interfaces. This
driver can utilize debugging capabilities and supported features as
exposed by the Power Management Controller. It also may perform some
tasks in the PMC in order to enable transition into the SLPS0 state.
It should be selected on all Intel platforms supported by the driver.
Supported features:
- SLP_S0_RESIDENCY counter
- PCH IP Power Gating status
- LTR Ignore / LTR Show
- MPHY/PLL gating status (Sunrisepoint PCH only)
- SLPS0 Debug registers (Cannonlake/Icelake PCH)
- Low Power Mode registers (Tigerlake and beyond)
- PMC quirks as needed to enable SLPS0/S0ix
# SPDX-License-Identifier: GPL-2.0
#
# Intel x86 Platform-Specific Drivers
#
intel_pmc_core-y := core.o
obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
intel_pmc_core_pltdrv-y := pltdrv.o
obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
......@@ -31,7 +31,7 @@
#include <asm/msr.h>
#include <asm/tsc.h>
#include "intel_pmc_core.h"
#include "core.h"
#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
#define ACPI_GET_LOW_MODE_REGISTERS 1
......
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