Commit fa0c10a5 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Linus Walleij

pinctrl: samsung: use 'int' for register masks in Exynos

The Special Function Registers on all Exynos SoC, including ARM64, are
32-bit wide, so entire driver uses matching functions like readl() or
writel().  On 64-bit ARM using unsigned long for register masks:
1. makes little sense as immediately after bitwise operation it will be
   cast to 32-bit value when calling writel(),
2. is actually error-prone because it might promote other operands to
   64-bit.

Addresses-Coverity: Unintentional integer overflow
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20210408195029.69974-1-krzysztof.kozlowski@canonical.comSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ea119e5a
...@@ -55,7 +55,7 @@ static void exynos_irq_mask(struct irq_data *irqd) ...@@ -55,7 +55,7 @@ static void exynos_irq_mask(struct irq_data *irqd)
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
unsigned long mask; unsigned int mask;
unsigned long flags; unsigned long flags;
raw_spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
...@@ -83,7 +83,7 @@ static void exynos_irq_unmask(struct irq_data *irqd) ...@@ -83,7 +83,7 @@ static void exynos_irq_unmask(struct irq_data *irqd)
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
unsigned long mask; unsigned int mask;
unsigned long flags; unsigned long flags;
/* /*
...@@ -483,7 +483,7 @@ static void exynos_irq_eint0_15(struct irq_desc *desc) ...@@ -483,7 +483,7 @@ static void exynos_irq_eint0_15(struct irq_desc *desc)
chained_irq_exit(chip, desc); chained_irq_exit(chip, desc);
} }
static inline void exynos_irq_demux_eint(unsigned long pend, static inline void exynos_irq_demux_eint(unsigned int pend,
struct irq_domain *domain) struct irq_domain *domain)
{ {
unsigned int irq; unsigned int irq;
...@@ -500,8 +500,8 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc) ...@@ -500,8 +500,8 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
{ {
struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip *chip = irq_desc_get_chip(desc);
struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
unsigned long pend; unsigned int pend;
unsigned long mask; unsigned int mask;
int i; int i;
chained_irq_enter(chip, desc); chained_irq_enter(chip, desc);
......
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