Commit fa3e4203 authored by Miaohe Lin's avatar Miaohe Lin Committed by Paolo Bonzini

KVM: x86/mmu: fix some comment typos

Fix some typos in comments.
Signed-off-by: default avatarMiaohe Lin <linmiaohe@huawei.com>
Reviewed-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20220913091725.35953-1-linmiaohe@huawei.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 0f9edb8c
...@@ -1894,7 +1894,7 @@ static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) ...@@ -1894,7 +1894,7 @@ static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
if (sp->role.invalid) if (sp->role.invalid)
return true; return true;
/* TDP MMU pages due not use the MMU generation. */ /* TDP MMU pages do not use the MMU generation. */
return !sp->tdp_mmu_page && return !sp->tdp_mmu_page &&
unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
} }
......
...@@ -188,7 +188,7 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask; ...@@ -188,7 +188,7 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
* should not modify the SPTE. * should not modify the SPTE.
* *
* Use a semi-arbitrary value that doesn't set RWX bits, i.e. is not-present on * Use a semi-arbitrary value that doesn't set RWX bits, i.e. is not-present on
* bot AMD and Intel CPUs, and doesn't set PFN bits, i.e. doesn't create a L1TF * both AMD and Intel CPUs, and doesn't set PFN bits, i.e. doesn't create a L1TF
* vulnerability. Use only low bits to avoid 64-bit immediates. * vulnerability. Use only low bits to avoid 64-bit immediates.
* *
* Only used by the TDP MMU. * Only used by the TDP MMU.
......
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