[ARM PATCH] 2338/1: IXP465 and IXDPG465 header file updates

Patch from Deepak Saxena

Update IXP4xx header files with new registers for IXP46x CPU family.

Replaces 2306/1

Signed-off-by: Deepak Saxena
Signed-off-by: Russell King

include/asm-arm/arch-ixp4xx/entry-macro.S

@@ -21,6 +21,19 @@
 		subs    \irqnr, \base, \irqnr
 
 1001:
+		/*
+		 * IXP465 has an upper IRQ status register
+		 */
+#if defined(CONFIG_CPU_IXP46X)
+		bne 	1002f
+		ldr	\irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
+		ldr	\irqstat, [\irqstat]		@ get upper interrupts
+		mov	\irqnr, #63
+		clz	\irqstat, \irqstat
+ 		cmp	\irqstat, #32
+		subne	\irqnr, \irqnr, \irqstat
+1002:
+#endif
 		.endm
 
 

include/asm-arm/arch-ixp4xx/hardware.h

@@ -27,6 +27,13 @@
 
 #define pcibios_assign_all_busses()	1
 
+#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__)
+extern unsigned int processor_id;
+#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
+#else
+#define	cpu_is_ixp465()	(0)
+#endif
+
 /* Register locations and bits */
 #include "ixp4xx-regs.h"
 

include/asm-arm/arch-ixp4xx/irqs.h

@@ -15,7 +15,6 @@
 #ifndef _ARCH_IXP4XX_IRQS_H_
 #define _ARCH_IXP4XX_IRQS_H_
 
-#define NR_IRQS			32
 
 #define IRQ_IXP4XX_NPEA		0
 #define IRQ_IXP4XX_NPEB		1
@@ -50,6 +49,27 @@
 #define IRQ_IXP4XX_SW_INT1	30
 #define IRQ_IXP4XX_SW_INT2	31
 
+#ifndef	CONFIG_CPU_IXP46X
+#define NR_IRQS			32
+#else
+
+/*
+ * IXP465 adds new sources
+ */
+#define IRQ_IXP4XX_USB_HOST	32
+#define IRQ_IXP4XX_I2C		33
+#define IRQ_IXP4XX_SSP		34
+#define IRQ_IXP4XX_TSYNC	35
+#define IRQ_IXP4XX_EAU_DONE	36
+#define IRQ_IXP4XX_SHA_DONE	37
+#define IRQ_IXP4XX_SWCP_PE	58
+#define IRQ_IXP4XX_QM_PE	60
+#define IRQ_IXP4XX_MCU_ECC	61
+#define IRQ_IXP4XX_EXP_PE	62
+
+#define NR_IRQS			64
+#endif
+
 #define	XSCALE_PMU_IRQ		(IRQ_IXP4XX_XSCALE_PMU)
 
 /*

include/asm-arm/arch-ixp4xx/ixp4xx-regs.h

@@ -129,6 +129,17 @@
 #define IXP4XX_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
 #define IXP4XX_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
 
+/*
+ * IXP465-only
+ */
+#define	IXP4XX_ICPR2_OFFSET	0x20 /* Interrupt Status 2 */
+#define	IXP4XX_ICMR2_OFFSET	0x24 /* Interrupt Enable 2 */
+#define	IXP4XX_ICLR2_OFFSET	0x28 /* Interrupt IRQ/FIQ Select 2 */
+#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
+#define IXP4XX_ICFP2_OFFSET	0x30 /* FIQ Status */
+#define IXP4XX_ICEEN_OFFSET	0x34 /* Error High Pri Enable */
+
+
 /*
  * Interrupt Controller Register Definitions.
  */
@@ -143,6 +154,12 @@
 #define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
 #define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
 #define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
+#define IXP4XX_ICPR2	IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
+#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
+#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
+#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
+#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
+#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
                                                                                 
 /*
  * Constants to make it easy to access GPIO registers
@@ -548,4 +565,19 @@
 
 #define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
 
+#ifndef __ASSEMBLY__
+static inline int cpu_is_ixp46x(void)
+{
+#ifdef CONFIG_CPU_IXP46X
+	unsigned int processor_id;
+
+	asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
+
+	if ((processor_id & 0xffffff00) == 0x69054200)
+		return 1;
+#endif
+	return 0;
+}
+#endif
+
 #endif