Commit faff3fcf authored by Olof Johansson's avatar Olof Johansson

Merge tag 'at91-5.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/late

AT91 SoC for 5.2

 - PM changes for SAM9X60

* tag 'at91-5.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: pm: do not disable/enable PLLA for ULP modes
  ARM: at91: pm: disable RC oscillator in ULP0
  ARM: at91: pm: add ULP1 support for SAM9X60
  ARM: at91: pm: add support for per SoC wakeup source configuration
  ARM: at91: pm: keep at91_pm_backup_init() only for SAMA5D2 SoCs
  ARM: at91: pm: initial PM support for SAM9X60
  dt-bindings: arm: atmel: add binding for SAM9X60 SoC
  ARM: at91: pm: introduce at91_soc_pm structure
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e40b0695 2725d70a
...@@ -25,6 +25,7 @@ compatible: must be one of: ...@@ -25,6 +25,7 @@ compatible: must be one of:
o "atmel,at91sam9n12" o "atmel,at91sam9n12"
o "atmel,at91sam9rl" o "atmel,at91sam9rl"
o "atmel,at91sam9xe" o "atmel,at91sam9xe"
o "microchip,sam9x60"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family: SoC family:
o "atmel,sama5d2" shall be extended with the specific SoC compatible: o "atmel,sama5d2" shall be extended with the specific SoC compatible:
......
...@@ -32,3 +32,21 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") ...@@ -32,3 +32,21 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
.init_machine = at91sam9_init, .init_machine = at91sam9_init,
.dt_compat = at91_dt_board_compat, .dt_compat = at91_dt_board_compat,
MACHINE_END MACHINE_END
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
...@@ -14,11 +14,13 @@ ...@@ -14,11 +14,13 @@
#ifdef CONFIG_PM #ifdef CONFIG_PM
extern void __init at91rm9200_pm_init(void); extern void __init at91rm9200_pm_init(void);
extern void __init at91sam9_pm_init(void); extern void __init at91sam9_pm_init(void);
extern void __init sam9x60_pm_init(void);
extern void __init sama5_pm_init(void); extern void __init sama5_pm_init(void);
extern void __init sama5d2_pm_init(void); extern void __init sama5d2_pm_init(void);
#else #else
static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91rm9200_pm_init(void) { }
static inline void __init at91sam9_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { }
static inline void __init sam9x60_pm_init(void) { }
static inline void __init sama5_pm_init(void) { } static inline void __init sama5_pm_init(void) { }
static inline void __init sama5d2_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { }
#endif #endif
......
This diff is collapsed.
...@@ -50,15 +50,6 @@ tmp2 .req r5 ...@@ -50,15 +50,6 @@ tmp2 .req r5
beq 1b beq 1b
.endm .endm
/*
* Wait until PLLA has locked.
*/
.macro wait_pllalock
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKA
beq 1b
.endm
/* /*
* Put the processor to enter the idle state * Put the processor to enter the idle state
*/ */
...@@ -178,11 +169,46 @@ ENDPROC(at91_backup_mode) ...@@ -178,11 +169,46 @@ ENDPROC(at91_backup_mode)
orr tmp1, tmp1, #AT91_PMC_KEY orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR] str tmp1, [pmc, #AT91_CKGR_MOR]
/* Save RC oscillator state */
ldr tmp1, [pmc, #AT91_PMC_SR]
str tmp1, .saved_osc_status
tst tmp1, #AT91_PMC_MOSCRCS
bne 1f
/* Turn off RC oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait main RC disabled done */
2: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCRCS
bne 2b
/* Wait for interrupt */ /* Wait for interrupt */
at91_cpu_idle 1: at91_cpu_idle
/* Turn on the crystal oscillator */ /* Restore RC oscillator state */
ldr tmp1, .saved_osc_status
tst tmp1, #AT91_PMC_MOSCRCS
beq 4f
/* Turn on RC oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR] ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait main RC stabilization */
3: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCRCS
beq 3b
/* Turn on the crystal oscillator */
4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCEN orr tmp1, tmp1, #AT91_PMC_MOSCEN
orr tmp1, tmp1, #AT91_PMC_KEY orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR] str tmp1, [pmc, #AT91_CKGR_MOR]
...@@ -197,8 +223,26 @@ ENDPROC(at91_backup_mode) ...@@ -197,8 +223,26 @@ ENDPROC(at91_backup_mode)
.macro at91_pm_ulp1_mode .macro at91_pm_ulp1_mode
ldr pmc, .pmc_base ldr pmc, .pmc_base
/* Switch the main clock source to 12-MHz RC oscillator */ /* Save RC oscillator state and check if it is enabled. */
ldr tmp1, [pmc, #AT91_PMC_SR]
str tmp1, .saved_osc_status
tst tmp1, #AT91_PMC_MOSCRCS
bne 2f
/* Enable RC oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR] ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait main RC stabilization */
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCRCS
beq 1b
/* Switch the main clock source to 12-MHz RC oscillator */
2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCSEL bic tmp1, tmp1, #AT91_PMC_MOSCSEL
bic tmp1, tmp1, #AT91_PMC_KEY_MASK bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY orr tmp1, tmp1, #AT91_PMC_KEY
...@@ -262,6 +306,25 @@ ENDPROC(at91_backup_mode) ...@@ -262,6 +306,25 @@ ENDPROC(at91_backup_mode)
str tmp1, [pmc, #AT91_PMC_MCKR] str tmp1, [pmc, #AT91_PMC_MCKR]
wait_mckrdy wait_mckrdy
/* Restore RC oscillator state */
ldr tmp1, .saved_osc_status
tst tmp1, #AT91_PMC_MOSCRCS
bne 3f
/* Disable RC oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait RC oscillator disable done */
4: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCRCS
bne 4b
3:
.endm .endm
ENTRY(at91_ulp_mode) ENTRY(at91_ulp_mode)
...@@ -279,14 +342,6 @@ ENTRY(at91_ulp_mode) ...@@ -279,14 +342,6 @@ ENTRY(at91_ulp_mode)
wait_mckrdy wait_mckrdy
/* Save PLLA setting and disable it */
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
str tmp1, .saved_pllar
mov tmp1, #AT91_PMC_PLLCOUNT
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
str tmp1, [pmc, #AT91_CKGR_PLLAR]
ldr r0, .pm_mode ldr r0, .pm_mode
cmp r0, #AT91_PM_ULP1 cmp r0, #AT91_PM_ULP1
beq ulp1_mode beq ulp1_mode
...@@ -301,18 +356,6 @@ ulp1_mode: ...@@ -301,18 +356,6 @@ ulp1_mode:
ulp_exit: ulp_exit:
ldr pmc, .pmc_base ldr pmc, .pmc_base
/* Restore PLLA setting */
ldr tmp1, .saved_pllar
str tmp1, [pmc, #AT91_CKGR_PLLAR]
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
bne 3f
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
beq 4f
3:
wait_pllalock
4:
/* /*
* Restore master clock setting * Restore master clock setting
*/ */
...@@ -465,8 +508,6 @@ ENDPROC(at91_sramc_self_refresh) ...@@ -465,8 +508,6 @@ ENDPROC(at91_sramc_self_refresh)
.word 0 .word 0
.saved_mckr: .saved_mckr:
.word 0 .word 0
.saved_pllar:
.word 0
.saved_sam9_lpr: .saved_sam9_lpr:
.word 0 .word 0
.saved_sam9_lpr1: .saved_sam9_lpr1:
...@@ -475,6 +516,8 @@ ENDPROC(at91_sramc_self_refresh) ...@@ -475,6 +516,8 @@ ENDPROC(at91_sramc_self_refresh)
.word 0 .word 0
.saved_sam9_mdr1: .saved_sam9_mdr1:
.word 0 .word 0
.saved_osc_status:
.word 0
ENTRY(at91_pm_suspend_in_sram_sz) ENTRY(at91_pm_suspend_in_sram_sz)
.word .-at91_pm_suspend_in_sram .word .-at91_pm_suspend_in_sram
...@@ -161,6 +161,7 @@ ...@@ -161,6 +161,7 @@
#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ #define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */
#define AT91_PMC_FSTT(n) BIT(n) #define AT91_PMC_FSTT(n) BIT(n)
#define AT91_PMC_RTTAL BIT(16)
#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ #define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ #define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ #define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */
......
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