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Commit fb249b27 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc-arm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC code updates from Arnd Bergmann:
 "There are two notable changes this time:

   - add a arch/arm/Kconfig.platforms file to simplify the platforms
     that have no code except their Kconfig file (Andrew Davis)

   - remove support for the ARM11MPCore CPU in the versatile/realview
     platform. Since this is the last remaining one after removing
     ox820, some core code can go as well (Linus Walleij)

  The other changes are minor cleanups and bugfixes"

* tag 'soc-arm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: davinci: always select CONFIG_CPU_ARM926T
  soc: pxa: ssp: fix casts
  ARM: debug: fix DEBUG_UNCOMPRESS help for !MULTIPLATFORM
  ARM: MAINTAINERS: drop empty entries for removed boards
  ARM: Delete ARM11MPCore perf leftovers
  ARM: mach-nspire: Rework support and directory structure
  ARM: mach-sunplus: Rework support and directory structure
  ARM: mach-airoha: Rework support and directory structure
  ARM: mach-moxart: Move MOXA ART support into Kconfig.platforms
  ARM: mach-uniphier: Move Socionext UniPhier support into Kconfig.platforms
  ARM: mach-rda: Move RDA Micro support into Kconfig.platforms
  ARM: mach-asm9260: Move ASM9260 support into Kconfig.platforms
  ARM: Kconfig: move platform selection into its own Kconfig file
  ARM: Delete ARM11MPCore (ARM11 ARMv6K SMP) support
  MAINTAINERS: add Marvell MBus driver to Marvell EBU SoCs support
  ARM: mxs: Do not search for "fsl,clkctrl"
  ARM: imx: Use device_get_match_data()
  MAINTAINERS: add omap bus drivers to OMAP2+ SUPPORT
  ARM: at91: pm: set soc_pm.data.mode in at91_pm_secure_init()
parents f6597d17 40974ee4
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MAINTAINERS
View file @ fb249b27
......@@ -2015,11 +2015,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd Fixes
N: clps711x
ARM/CIRRUS LOGIC EDB9315A MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
M: Hartley Sweeten <hsweeten@visionengravers.com>
M: Alexander Sverdlin <alexander.sverdlin@gmail.com>
......@@ -2305,6 +2300,7 @@ F: arch/arm/mach-dove/
F: arch/arm/mach-mv78xx0/
F: arch/arm/mach-orion5x/
F: arch/arm/plat-orion/
F: drivers/bus/mvebu-mbus.c
F: drivers/soc/dove/
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
......@@ -2821,7 +2817,6 @@ F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.ya
F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
F: arch/arm/boot/dts/sunplus/
F: arch/arm/configs/sp7021_*defconfig
F: arch/arm/mach-sunplus/
F: drivers/clk/clk-sp7021.c
F: drivers/irqchip/irq-sp7021-intc.c
F: drivers/reset/reset-sunplus.c
......@@ -2837,11 +2832,6 @@ F: arch/arm/boot/dts/synaptics/
F: arch/arm/mach-berlin/
F: arch/arm64/boot/dts/synaptics/
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/TEGRA HDMI CEC SUBSYSTEM SUPPORT
M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
L: linux-tegra@vger.kernel.org
......@@ -2858,11 +2848,6 @@ L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: arch/arm64/boot/dts/tesla/
ARM/TETON BGA MACHINE SUPPORT
M: "Mark F. Brown" <mark.brown314@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/TEXAS INSTRUMENT AEMIF/EMIF DRIVERS
M: Santosh Shilimkar <ssantosh@kernel.org>
L: linux-kernel@vger.kernel.org
......@@ -2941,7 +2926,6 @@ F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml
F: arch/arm/boot/dts/socionext/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
F: arch/arm64/boot/dts/socionext/uniphier*
F: drivers/bus/uniphier-system-bus.c
......@@ -15874,6 +15858,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
F: Documentation/devicetree/bindings/arm/ti/omap.yaml
F: arch/arm/configs/omap2plus_defconfig
F: arch/arm/mach-omap2/
F: drivers/bus/omap*.[ch]
F: drivers/bus/ti-sysc.c
F: drivers/gpio/gpio-tps65219.c
F: drivers/i2c/busses/i2c-omap.c
......@@ -19839,11 +19824,6 @@ F: Documentation/devicetree/bindings/display/simple-framebuffer.yaml
F: drivers/video/fbdev/simplefb.c
F: include/linux/platform_data/simplefb.h
SIMTEC EB110ATX (Chalice CATS)
M: Simtec Linux Team <linux@simtec.co.uk>
S: Supported
W: http://www.simtec.co.uk/products/EB110ATX/
SIOX
M: Thorsten Scherer <t.scherer@eckelmann.de>
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
......
arch/arm/Kconfig
View file @ fb249b27
......@@ -340,83 +340,7 @@ config ARCH_MULTIPLATFORM
Selecting N here allows using those options, including
DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
menu "Platform selection"
depends on MMU
comment "CPU Core family selection"
config ARCH_MULTI_V4
bool "ARMv4 based platforms (FA526, StrongARM)"
depends on !ARCH_MULTI_V6_V7
# https://github.com/llvm/llvm-project/issues/50764
depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on !ARCH_MULTI_V6_V7
# https://github.com/llvm/llvm-project/issues/50764
depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
CPU_ARM925T || CPU_ARM940T)
config ARCH_MULTI_V5
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
config ARCH_MULTI_V4_V5
bool
config ARCH_MULTI_V6
bool "ARMv6 based platforms (ARM11)"
select ARCH_MULTI_V6_V7
select CPU_V6K
config ARCH_MULTI_V7
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
default y
select ARCH_MULTI_V6_V7
select CPU_V7
select HAVE_SMP
config ARCH_MULTI_V6_V7
bool
select MIGHT_HAVE_CACHE_L2X0
config ARCH_MULTI_CPU_AUTO
def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
select ARCH_MULTI_V5
endmenu
config ARCH_VIRT
bool "Dummy Virtual Machine"
depends on ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_GIC_V2M if PCI
select ARM_GIC_V3
select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
config ARCH_AIROHA
bool "Airoha SoC Support"
depends on ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_GIC_V3
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
help
Support for Airoha EN7523 SoCs
source "arch/arm/Kconfig.platforms"
#
# This is sorted alphabetically by mach-* pathname. However, plat-*
......@@ -429,8 +353,6 @@ source "arch/arm/mach-alpine/Kconfig"
source "arch/arm/mach-artpec/Kconfig"
source "arch/arm/mach-asm9260/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-at91/Kconfig"
......@@ -479,8 +401,6 @@ source "arch/arm/mach-milbeaut/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-mstar/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
......@@ -493,8 +413,6 @@ source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
......@@ -505,8 +423,6 @@ source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
source "arch/arm/mach-rpc/Kconfig"
......@@ -529,14 +445,10 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-sunplus/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
......
arch/arm/Kconfig.debug
View file @ fb249b27
......@@ -1809,15 +1809,8 @@ config DEBUG_UNCOMPRESS
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
help
This option influences the normal decompressor output for
multiplatform kernels. Normally, multiplatform kernels disable
decompressor output because it is not possible to know where to
send the decompressor output.
When this option is set, the selected DEBUG_LL output method
will be re-used for normal decompressor output on multiplatform
kernels.
Say Y here to enable debug output in the decompressor code, using
the selected DEBUG_LL output method.
config UNCOMPRESS_INCLUDE
string
......
arch/arm/Kconfig.platforms 0 → 100644
View file @ fb249b27
# SPDX-License-Identifier: GPL-2.0-only
menu "Platform selection"
depends on MMU
comment "CPU Core family selection"
config ARCH_MULTI_V4
bool "ARMv4 based platforms (FA526, StrongARM)"
depends on !ARCH_MULTI_V6_V7
# https://github.com/llvm/llvm-project/issues/50764
depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on !ARCH_MULTI_V6_V7
# https://github.com/llvm/llvm-project/issues/50764
depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
CPU_ARM925T || CPU_ARM940T)
config ARCH_MULTI_V5
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
config ARCH_MULTI_V4_V5
bool
config ARCH_MULTI_V6
bool "ARMv6 based platforms (ARM11)"
select ARCH_MULTI_V6_V7
select CPU_V6K
config ARCH_MULTI_V7
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
default y
select ARCH_MULTI_V6_V7
select CPU_V7
select HAVE_SMP
config ARCH_MULTI_V6_V7
bool
select MIGHT_HAVE_CACHE_L2X0
config ARCH_MULTI_CPU_AUTO
def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
select ARCH_MULTI_V5
endmenu
config ARCH_VIRT
bool "Dummy Virtual Machine"
depends on ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_GIC_V2M if PCI
select ARM_GIC_V3
select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
config ARCH_AIROHA
bool "Airoha SoC Support"
depends on ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_GIC_V3
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
help
Support for Airoha EN7523 SoCs
config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select ASM9260_TIMER
help
Support for Alphascale ASM9260 based platform.
menuconfig ARCH_MOXART
bool "MOXA ART SoC"
depends on ARCH_MULTI_V4
depends on CPU_LITTLE_ENDIAN
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010
select FTTMR010_TIMER
select GPIOLIB
select PHYLIB if NETDEVICES
help
Say Y here if you want to run your kernel on hardware with a
MOXA ART SoC.
The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
if ARCH_MOXART
config MACH_UC7112LX
bool "MOXA UC-7112-LX"
depends on ARCH_MOXART
help
Say Y here if you intend to run this kernel on a MOXA
UC-7112-LX embedded computer.
endif
config ARCH_NSPIRE
bool "TI-NSPIRE based"
depends on ARCH_MULTI_V4T
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select GENERIC_IRQ_CHIP
select ARM_AMBA
select ARM_VIC
select ARM_TIMER_SP804
select NSPIRE_TIMER
select POWER_RESET
select POWER_RESET_SYSCON
help
This enables support for systems using the TI-NSPIRE CPU
config ARCH_RDA
bool "RDA Micro SoCs"
depends on ARCH_MULTI_V7
select RDA_INTC
select RDA_TIMER
help
This enables support for the RDA Micro 8810PL SoC family.
menuconfig ARCH_SUNPLUS
bool "Sunplus SoCs"
depends on ARCH_MULTI_V7
help
Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
such as the Banana Pi BPI-F2S development board (and derivatives).
(<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
(<https://tibbo.com/store/plus1.html>)
if ARCH_SUNPLUS
config SOC_SP7021
bool "Sunplus SP7021 SoC support"
default ARCH_SUNPLUS
select HAVE_ARM_ARCH_TIMER
select ARM_GIC
select ARM_PSCI
select PINCTRL
select PINCTRL_SPPCTL
select SERIAL_SUNPLUS if TTY
select SERIAL_SUNPLUS_CONSOLE if TTY
help
Support for Sunplus SP7021 SoC. It is based on ARM 4-core
Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
Ethernet, etc.), FPGA interface, chip-to-chip bus.
It is designed for industrial control.
endif
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GLOBAL_TIMER
select ARM_GIC
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select PINCTRL
select RESET_CONTROLLER
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
arch/arm/Makefile
View file @ fb249b27
......@@ -167,7 +167,6 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_ACTIONS) += actions
machine-$(CONFIG_ARCH_AIROHA) += airoha
machine-$(CONFIG_ARCH_ALPINE) += alpine
machine-$(CONFIG_ARCH_ARTPEC) += artpec
machine-$(CONFIG_ARCH_ASPEED) += aspeed
......@@ -192,7 +191,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
......@@ -202,7 +200,6 @@ machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_MSTARV7) += mstar
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
......@@ -218,7 +215,6 @@ machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32
machine-$(CONFIG_ARCH_SUNPLUS) += sunplus
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += ux500
......
arch/arm/kernel/perf_event_v6.c
View file @ fb249b27
......@@ -113,69 +113,6 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
};
enum armv6mpcore_perf_types {
ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
};
/*
* The hardware events that we support. We do support cache operations but
* we have harvard caches and no way to combine instruction and data
* accesses/misses in hardware.
*/
static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
PERF_MAP_ALL_UNSUPPORTED,
[PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
};
static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
PERF_CACHE_MAP_ALL_UNSUPPORTED,
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
/*
* The ARM performance counters can count micro DTLB misses, micro ITLB
* misses and main TLB misses. There isn't an event for TLB misses, so
* use the micro misses here and if users want the main TLB misses they
* can use a raw counter.
*/
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
};
static inline unsigned long
armv6_pmcr_read(void)
{
......@@ -438,33 +375,6 @@ static void armv6pmu_disable_event(struct perf_event *event)
armv6_pmcr_write(val);
}
static void armv6mpcore_pmu_disable_event(struct perf_event *event)
{
unsigned long val, mask, evt = 0;
struct hw_perf_event *hwc = &event->hw;
int idx = hwc->idx;
if (ARMV6_CYCLE_COUNTER == idx) {
mask = ARMV6_PMCR_CCOUNT_IEN;
} else if (ARMV6_COUNTER0 == idx) {
mask = ARMV6_PMCR_COUNT0_IEN;
} else if (ARMV6_COUNTER1 == idx) {
mask = ARMV6_PMCR_COUNT1_IEN;
} else {
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
return;
}
/*
* Unlike UP ARMv6, we don't have a way of stopping the counters. We
* simply disable the interrupt reporting.
*/
val = armv6_pmcr_read();
val &= ~mask;
val |= evt;
armv6_pmcr_write(val);
}
static int armv6_map_event(struct perf_event *event)
{
return armpmu_map_event(event, &armv6_perf_map,
......@@ -507,40 +417,7 @@ static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu)
return 0;
}
/*
* ARMv6mpcore is almost identical to single core ARMv6 with the exception
* that some of the events have different enumerations and that there is no
* *hack* to stop the programmable counters. To stop the counters we simply
* disable the interrupt reporting and update the event. When unthrottling we
* reset the period and enable the interrupt reporting.
*/
static int armv6mpcore_map_event(struct perf_event *event)
{
return armpmu_map_event(event, &armv6mpcore_perf_map,
&armv6mpcore_perf_cache_map, 0xFF);
}
static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "armv6_11mpcore";
cpu_pmu->handle_irq = armv6pmu_handle_irq;
cpu_pmu->enable = armv6pmu_enable_event;
cpu_pmu->disable = armv6mpcore_pmu_disable_event;
cpu_pmu->read_counter = armv6pmu_read_counter;
cpu_pmu->write_counter = armv6pmu_write_counter;
cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx;
cpu_pmu->start = armv6pmu_start;
cpu_pmu->stop = armv6pmu_stop;
cpu_pmu->map_event = armv6mpcore_map_event;
cpu_pmu->num_events = 3;
return 0;
}
static const struct of_device_id armv6_pmu_of_device_ids[] = {
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
{ /* sentinel value */ }
......@@ -550,7 +427,6 @@ static const struct pmu_probe_info armv6_pmu_probe_table[] = {
ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init),
ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init),
ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init),
ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init),
{ /* sentinel value */ }
};
......
arch/arm/mach-airoha/Makefile deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
obj-y += airoha.o
arch/arm/mach-airoha/airoha.c deleted 100644 → 0
View file @ f6597d17
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device Tree support for Airoha SoCs
*
* Copyright (c) 2022 Felix Fietkau <nbd@nbd.name>
*/
#include <asm/mach/arch.h>
static const char * const airoha_board_dt_compat[] = {
"airoha,en7523",
NULL,
};
DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)")
.dt_compat = airoha_board_dt_compat,
MACHINE_END
arch/arm/mach-asm9260/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select ASM9260_TIMER
help
Support for Alphascale ASM9260 based platform.
arch/arm/mach-at91/pm.c
View file @ fb249b27
......@@ -1103,6 +1103,7 @@ static void __init at91_pm_secure_init(void)
if (res.a0 == 0) {
pr_info("AT91: Secure PM: suspend mode set to %s\n",
pm_modes[suspend_mode].pattern);
soc_pm.data.mode = suspend_mode;
return;
}
......@@ -1112,6 +1113,7 @@ static void __init at91_pm_secure_init(void)
res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
if (res.a0 == 0) {
pr_warn("AT91: Secure PM: failed to get default mode\n");
soc_pm.data.mode = -1;
return;
}
......@@ -1119,6 +1121,7 @@ static void __init at91_pm_secure_init(void)
pm_modes[suspend_mode].pattern);
soc_pm.data.suspend_mode = res.a1;
soc_pm.data.mode = soc_pm.data.suspend_mode;
}
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
......
arch/arm/mach-davinci/Kconfig
View file @ fb249b27
......@@ -4,6 +4,7 @@ menuconfig ARCH_DAVINCI
bool "TI DaVinci"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select DAVINCI_TIMER
select ZONE_DMA
select PM_GENERIC_DOMAINS if PM
......
arch/arm/mach-imx/mmdc.c
View file @ fb249b27
......@@ -13,7 +13,8 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/perf_event.h>
#include <linux/slab.h>
......@@ -103,7 +104,7 @@ struct mmdc_pmu {
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
struct fsl_mmdc_devtype_data *devtype_data;
const struct fsl_mmdc_devtype_data *devtype_data;
struct clk *mmdc_ipg_clk;
};
......@@ -474,8 +475,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
struct mmdc_pmu *pmu_mmdc;
char *name;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
if (!pmu_mmdc) {
......@@ -507,7 +506,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
}
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
pmu_mmdc->devtype_data = device_get_match_data(&pdev->dev);
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
......
arch/arm/mach-moxart/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MOXART
bool "MOXA ART SoC"
depends on ARCH_MULTI_V4
depends on CPU_LITTLE_ENDIAN
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010
select FTTMR010_TIMER
select GPIOLIB
select PHYLIB if NETDEVICES
help
Say Y here if you want to run your kernel on hardware with a
MOXA ART SoC.
The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
if ARCH_MOXART
config MACH_UC7112LX
bool "MOXA UC-7112-LX"
depends on ARCH_MOXART
help
Say Y here if you intend to run this kernel on a MOXA
UC-7112-LX embedded computer.
endif
arch/arm/mach-moxart/Makefile deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
# Object file lists.
obj-$(CONFIG_MACH_UC7112LX) += moxart.o
arch/arm/mach-moxart/moxart.c deleted 100644 → 0
View file @ f6597d17
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/arm/mach-moxart/moxart.c
*
* (C) Copyright 2013, Jonas Jensen <jonas.jensen@gmail.com>
*/
arch/arm/mach-mxs/mach-mxs.c
View file @ fb249b27
......@@ -356,7 +356,9 @@ static int __init mxs_restart_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
if (!np)
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
reset_addr = of_iomap(np, 0);
if (!reset_addr)
return -ENODEV;
......
arch/arm/mach-nspire/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_NSPIRE
bool "TI-NSPIRE based"
depends on ARCH_MULTI_V4T
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select GENERIC_IRQ_CHIP
select ARM_AMBA
select ARM_VIC
select ARM_TIMER_SP804
select NSPIRE_TIMER
select POWER_RESET
select POWER_RESET_SYSCON
help
This enables support for systems using the TI-NSPIRE CPU
arch/arm/mach-nspire/Makefile deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
obj-y += nspire.o
arch/arm/mach-nspire/nspire.c deleted 100644 → 0
View file @ f6597d17
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
*/
#include <asm/mach/arch.h>
static const char *const nspire_dt_match[] __initconst = {
"ti,nspire",
"ti,nspire-cx",
"ti,nspire-tp",
"ti,nspire-clp",
NULL,
};
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
.dt_compat = nspire_dt_match,
MACHINE_END
arch/arm/mach-rda/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_RDA
bool "RDA Micro SoCs"
depends on ARCH_MULTI_V7
select RDA_INTC
select RDA_TIMER
help
This enables support for the RDA Micro 8810PL SoC family.
arch/arm/mach-sunplus/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
menuconfig ARCH_SUNPLUS
bool "Sunplus SoCs"
depends on ARCH_MULTI_V7
help
Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
such as the Banana Pi BPI-F2S development board (and derivatives).
(<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
(<https://tibbo.com/store/plus1.html>)
config SOC_SP7021
bool "Sunplus SP7021 SoC support"
depends on ARCH_SUNPLUS
default ARCH_SUNPLUS
select HAVE_ARM_ARCH_TIMER
select ARM_GIC
select ARM_PSCI
select PINCTRL
select PINCTRL_SPPCTL
select SERIAL_SUNPLUS if TTY
select SERIAL_SUNPLUS_CONSOLE if TTY
help
Support for Sunplus SP7021 SoC. It is based on ARM 4-core
Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
Ethernet, etc.), FPGA interface, chip-to-chip bus.
It is designed for industrial control.
arch/arm/mach-sunplus/Makefile deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-$(CONFIG_SOC_SP7021) += sp7021.o
arch/arm/mach-sunplus/sp7021.c deleted 100644 → 0
View file @ f6597d17
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) Sunplus Technology Co., Ltd.
* All rights reserved.
*/
#include <linux/kernel.h>
#include <asm/mach/arch.h>
static const char *sp7021_compat[] __initconst = {
"sunplus,sp7021",
NULL
};
DT_MACHINE_START(SP7021_DT, "SP7021")
.dt_compat = sp7021_compat,
MACHINE_END
arch/arm/mach-uniphier/Kconfig deleted 100644 → 0
View file @ f6597d17
# SPDX-License-Identifier: GPL-2.0
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GLOBAL_TIMER
select ARM_GIC
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select PINCTRL
select RESET_CONTROLLER
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
arch/arm/mach-versatile/Kconfig
View file @ fb249b27
......@@ -201,23 +201,6 @@ config REALVIEW_EB_A9MP
Enable support for the Cortex-A9MPCore tile fitted to the
Realview(R) Emulation Baseboard platform.
config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
select HAVE_SMP
help
Enable support for the ARM11MPCore tile fitted to the Realview(R)
Emulation Baseboard platform.
config MACH_REALVIEW_PB11MP
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
depends on ARCH_MULTI_V6
select HAVE_SMP
help
Include support for the ARM(R) RealView(R) Platform Baseboard for
the ARM11MPCore. This platform has an on-board ARM11MPCore and has
support for PCI-E and Compact Flash.
# ARMv6 CPU without K extensions, but does have the new exclusive ops
config MACH_REALVIEW_PB1176
bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
......
arch/arm/mach-versatile/platsmp-realview.c
View file @ fb249b27
......@@ -18,6 +18,11 @@
#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
static const struct of_device_id realview_scu_match[] = {
/*
* The ARM11MP SCU compatible is only provided as fallback for
* old RealView EB Cortex-A9 device trees that were using this
* compatible by mistake.
*/
{ .compatible = "arm,arm11mp-scu", },
{ .compatible = "arm,cortex-a9-scu", },
{ .compatible = "arm,cortex-a5-scu", },
......@@ -27,7 +32,6 @@ static const struct of_device_id realview_scu_match[] = {
static const struct of_device_id realview_syscon_match[] = {
{ .compatible = "arm,core-module-integrator", },
{ .compatible = "arm,realview-eb-syscon", },
{ .compatible = "arm,realview-pb11mp-syscon", },
{ .compatible = "arm,realview-pbx-syscon", },
{ },
};
......
arch/arm/mach-versatile/realview.c
View file @ fb249b27
......@@ -9,7 +9,6 @@
static const char *const realview_dt_platform_compat[] __initconst = {
"arm,realview-eb",
"arm,realview-pb1176",
"arm,realview-pb11mp",
"arm,realview-pba8",
"arm,realview-pbx",
NULL,
......
arch/arm/mm/Kconfig
View file @ fb249b27
......@@ -937,24 +937,6 @@ config VDSO
You must have glibc 2.22 or later for programs to seamlessly
take advantage of this.
config DMA_CACHE_RWFO
bool "Enable read/write for ownership DMA cache maintenance"
depends on CPU_V6K && SMP
default y
help
The Snoop Control Unit on ARM11MPCore does not detect the
cache maintenance operations and the dma_{map,unmap}_area()
functions may leave stale cache entries on other CPUs. By
enabling this option, Read or Write For Ownership in the ARMv6
DMA cache maintenance functions is performed. These LDR/STR
instructions change the cache line state to shared or modified
so that the cache operation has the desired effect.
Note that the workaround is only valid on processors that do
not perform speculative loads into the D-cache. For such
processors, if cache maintenance operations are not broadcast
in hardware, other workarounds are needed (e.g. cache
maintenance broadcasting in software via FIQ).
config OUTER_CACHE
bool
......
arch/arm/mm/cache-v6.S
View file @ fb249b27
......@@ -201,10 +201,6 @@ ENTRY(v6_flush_kern_dcache_area)
* - end - virtual end address of region
*/
v6_dma_inv_range:
#ifdef CONFIG_DMA_CACHE_RWFO
ldrb r2, [r0] @ read for ownership
strb r2, [r0] @ write for ownership
#endif
tst r0, #D_CACHE_LINE_SIZE - 1
bic r0, r0, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
......@@ -213,10 +209,6 @@ v6_dma_inv_range:
mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
#endif
tst r1, #D_CACHE_LINE_SIZE - 1
#ifdef CONFIG_DMA_CACHE_RWFO
ldrbne r2, [r1, #-1] @ read for ownership
strbne r2, [r1, #-1] @ write for ownership
#endif
bic r1, r1, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
......@@ -231,10 +223,6 @@ v6_dma_inv_range:
#endif
add r0, r0, #D_CACHE_LINE_SIZE
cmp r0, r1
#ifdef CONFIG_DMA_CACHE_RWFO
ldrlo r2, [r0] @ read for ownership
strlo r2, [r0] @ write for ownership
#endif
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
......@@ -248,9 +236,6 @@ v6_dma_inv_range:
v6_dma_clean_range:
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef CONFIG_DMA_CACHE_RWFO
ldr r2, [r0] @ read for ownership
#endif
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c10, 1 @ clean D line
#else
......@@ -269,10 +254,6 @@ v6_dma_clean_range:
* - end - virtual end address of region
*/
ENTRY(v6_dma_flush_range)
#ifdef CONFIG_DMA_CACHE_RWFO
ldrb r2, [r0] @ read for ownership
strb r2, [r0] @ write for ownership
#endif
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
......@@ -282,10 +263,6 @@ ENTRY(v6_dma_flush_range)
#endif
add r0, r0, #D_CACHE_LINE_SIZE
cmp r0, r1
#ifdef CONFIG_DMA_CACHE_RWFO
ldrblo r2, [r0] @ read for ownership
strblo r2, [r0] @ write for ownership
#endif
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
......@@ -301,13 +278,7 @@ ENTRY(v6_dma_map_area)
add r1, r1, r0
teq r2, #DMA_FROM_DEVICE
beq v6_dma_inv_range
#ifndef CONFIG_DMA_CACHE_RWFO
b v6_dma_clean_range
#else
teq r2, #DMA_TO_DEVICE
beq v6_dma_clean_range
b v6_dma_flush_range
#endif
ENDPROC(v6_dma_map_area)
/*
......@@ -317,11 +288,9 @@ ENDPROC(v6_dma_map_area)
* - dir - DMA direction
*/
ENTRY(v6_dma_unmap_area)
#ifndef CONFIG_DMA_CACHE_RWFO
add r1, r1, r0
teq r2, #DMA_TO_DEVICE
bne v6_dma_inv_range
#endif
ret lr
ENDPROC(v6_dma_unmap_area)
......
drivers/soc/pxa/ssp.c
View file @ fb249b27
......@@ -152,11 +152,11 @@ static int pxa_ssp_probe(struct platform_device *pdev)
if (dev->of_node) {
const struct of_device_id *id =
of_match_device(of_match_ptr(pxa_ssp_of_ids), dev);
ssp->type = (int) id->data;
ssp->type = (uintptr_t) id->data;
} else {
const struct platform_device_id *id =
platform_get_device_id(pdev);
ssp->type = (int) id->driver_data;
ssp->type = id->driver_data;
/* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
* starts from 0, do a translation here
......
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