Commit fdcb613d authored by Hans de Goede's avatar Hans de Goede Committed by Thierry Reding

ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices

The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set
of private registers at offset 0x800, the current lpss_device_desc for
them already sets the LPSS_SAVE_CTX flag to have these saved/restored
over device-suspend, but the current lpss_device_desc was not setting
the prv_offset field, leading to the regular device registers getting
saved/restored instead.

This is causing the PWM controller to no longer work, resulting in a black
screen,  after a suspend/resume on systems where the firmware clears the
APB clock and reset bits at offset 0x804.

This commit fixes this by properly setting prv_offset to 0x800 for
the PWM devices.

Cc: stable@vger.kernel.org
Fixes: e1c74817 ("ACPI / LPSS: Add Intel BayTrail ACPI mode PWM")
Fixes: 1bfbd8eb ("ACPI / LPSS: Add ACPI IDs for Intel Braswell")
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarRafael J . Wysocki <rjw@rjwysocki.net>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 1d375b58
...@@ -229,11 +229,13 @@ static const struct lpss_device_desc lpt_sdio_dev_desc = { ...@@ -229,11 +229,13 @@ static const struct lpss_device_desc lpt_sdio_dev_desc = {
static const struct lpss_device_desc byt_pwm_dev_desc = { static const struct lpss_device_desc byt_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX, .flags = LPSS_SAVE_CTX,
.prv_offset = 0x800,
.setup = byt_pwm_setup, .setup = byt_pwm_setup,
}; };
static const struct lpss_device_desc bsw_pwm_dev_desc = { static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
.prv_offset = 0x800,
.setup = bsw_pwm_setup, .setup = bsw_pwm_setup,
}; };
......
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